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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Issue A
Change Location Affects

First release

- -

Table C.2. Differences between Issue A and Issue B
Change Location Affects

Cluster device shutdown sequence updated

Cluster shutdown mode without system driven L2 flush All revisions
Revision information updated. System Control r0p1
GIC programmers model
ETM register descriptions
Peripheral Identification Register 2
Peripheral Identification Register 2
Peripheral Identification Register 2
Peripheral Identification Register 2
ID_AA64MMFR0_EL1 description updated AArch64 Memory Model Feature Register 0, EL1 All revisions
ACTLR_EL3 description updated.

Auxiliary Control Register, EL3

All revisions
CPUECTLR_EL1 description updated. CPU Extended Control Register, EL1 All revisions
ACTLR description updated.

Auxiliary Control Register

All revisions
Updated Encodings for ACE master interface Table 7.6 All revisions
Table 7.7
List of ACE transactions updated. ACE transfers All revisions
Shareability description updated ACP user signals All revisions
Table A.29
Table A.32
GIC signal descriptions updated Generic Interrupt Controller signals All revisions
CPUECTLR bit assignment table updated Table 4.255 All revisions

Table C.3. Differences between Issue B and Issue C
Change Location Affects
Change Multiprocessor, Processor to Cluster, Core naming convention Throughout document All revisions
Removed reference to T32EE (ThumbEE) ARM architecture All revisions
Updated notes in descriptions of PCLKENDBG, ATCLKEN and CNTCLKEN signals Clocks All revisions
Updated list of supported core power states Table 2.5 All revisions
Revision information updated. System Control r0p2
GIC programmers model
ETM register descriptions
Peripheral Identification Register 2
Peripheral Identification Register 2
Peripheral Identification Register 2
Peripheral Identification Register 2
Updated some register summary information

AArch64 register summary

AArch32 register summary

All revisions
Updated TTBR1 register description

Translation Table Base Register 1

Translation Table Base Register 1

All revisions
Updated CPUMERRSR_EL1 and CPUMERRSR descriptions

Table 4.126

Table 4.157

Table 4.256

All revisions
Removed DACR from list of c4 registers c4 registers All revisions
Updated GIC system registers in AArch32 summary tables

Table 4.156

c4 registers

c12 registers

All revisions
Added a new table, AArch64 registers used to access internal memory Table 6.4 All revisions
Updated Return stack predictions Return stack predictions All revisions
Update list of AArch64 registers used to access internal memory Table 6.4 All revisions
Added a new table, MOESI states Table 6.8 All revisions
Updated ACE transfer information ACE transfers All revisions
Updated ACE and CHI master interface write issuing capability

Table 7.5

Table 7.11

All revisions
Updated AXI privilege information AXI privilege information All revisions
Register names changed in the ROM table Peripheral Identification Registers summary Table 11.33 All revisions
Updated PMU register summary table Table 12.9 All revisions
Peripheral identification and Component identification register names changed in Memory-mapped PMU register summary Table 12.15 All revisions
Updated ETM exception level information Table 13.1 All revisions
Updated ETM programming diagram Figure 13.2 All revisions
Updated ETM register purpose and constraint information Throughout ETM register descriptions All revisions
Updated ETM register descriptions

Table 13.37

Table 13.46

All revisions
Updated TRCITIATBOUTR bit assignments Integration Instruction ATB Out Register All revisions

TRCITIATBOUTR.BYTES description updated

Table 13.55 All revisions

TRCDEVAFF0 description updated to match MPIDR

Device Affinity Register 0 All revisions
Updated sequence of operations in section 11.10.4 (Changing the authentication signals) Changing the authentication signals All revisions

Table C.4. Differences between Issue C and Issue D
Change Location Affects
Updated descriptions of Memory Attribute Indirection Registers

Memory Attribute Indirection Register, EL1

Memory Attribute Indirection Register, EL2

Memory Attribute Indirection Register, EL3

Memory Attribute Indirection Registers 0 and 1

All revisions
Instruction mnemonic updated 64-bit registers All revisions
Added note to CPUECTLR.SMPEN bit description Table 4.255 All revisions
SELx signal reduced from 6 bits to 5 bits

Figure 13.21

Table 13.22

All revisions
Updated number of external inputs to trace unit

Table 13.39

All revisions
Footnote added to SAMMNBASE[39,24] description

Table A.17

All revisions

Table C.5. Differences between Issue D and Issue E
Change Location Affects
Revision information updated. Throughout document r0p3
Updated description of power states

Table 2.4

Table 2.5

All revisions
Added cache operations to register summary tables

AArch64 cache maintenance operations

AArch64 TLB maintenance operations

AArch64 address translation operations

AArch64 miscellaneous operations

AArch64 EL2 TLB maintenance operations

c7 System operations

c8 System operations

All revisions
Updated reset value for HCR_EL2 Table 4.13 All revisions
Updated AArch64 GIC register summary table Table 4.15 All revisions
Removed reference to ICC_SEIEN_EL1 register Table 4.15 All revisions
Updated reset value for CPUACTLR_EL1 Table 4.17 All revisions
Added CPUACTLR_EL1.ENDCCASCI bit description. CPU Auxiliary Control Register, EL1 r0p3
Updated reset value for PMCEID0 Table 4.153 All revisions
Added ICH_VSEIR to register summary table Table 4.156 All revisions
Updated cross reference to TTBCR(NS) in TCR_EL1 description Translation Table Base Control Register All revisions
Added CPUACTLR.ENDCCASCI bit description. CPU Auxiliary Control Register r0p3
Added description of EDRCR register External Debug Reserve Control Register All revisions
Updated CPU 0 debug entry in “Address mapping for APB components” table Table 11.28 All revisions
Updated description of GICCDISABLE signal Table A.4 All revisions
Updated description of DBGPWRUPREQ signal Table A.6 All revisions

Table C.6. Differences between Issue E and Issue F
Change Location Affects
Updated description of Dormant mode Dormant mode All revisions
Renamed ICH_ELSR_EL2 to ICH_ELRSR_EL2 Table 4.15 All revisions
Removed register ICH_VSEIR_EL2 Table 4.15 All revisions
Updated TCR_EL1.TG0 and TCR_EL1.TG1 bit descriptions Table 4.88 All revisions
Updated ESR_EL1, ESR_EL2, and ESR_EL3 register descriptions to qualify the ISS field contents, and their dependency on the nSEI, nVSEI, and nREI signals. Exception Syndrome Register, EL1, Exception Syndrome Register, EL2, Exception Syndrome Register, EL3 All revisions
Renamed ICH_ELSR to ICH_ELRSR Table 4.156 All revisions
Updated the Configuration sections of registers CSSELR, SCTLR, TTBCR, DACR, DFSR, IFSR, PRRR, MAIR0, MAIR1, NMRR and VBAR. Cache Size Selection Register, System Control Register, Translation Table Base Control Register, Domain Access Control Register, Data Fault Status Register, Instruction Fault Status Register, Primary Region Remap Register, Memory Attribute Indirection Registers 0 and 1, Normal Memory Remap Register, and Vector Base Address Register. All revisions
Qualified instruction cache speculative memory accesses for pages with Device memory type attributes. Instruction cache speculative memory accesses All revisions
Updated the instruction cache disable behavior Instruction cache disabled behavior All revisions
Updated description of uncorrectable errors Error reporting All revisions
Renamed GICH_ELSR0 to GICH_ELRSR0 Table 9.5 All revisions
Updated DBGWCRn_EL1 bit field descriptions Table 11.5 All revisions
Updated CBRRQ.EDRCR bit description Table 11.12 All revisions
Updated the event name descriptions Table 12.28 All revisions
Updated description of WARMRSTREQ[CN:0] signal Table A.2 All revisions
Updated description of GICCDISABLE signal Table A.4 All revisions
Revision information updated Main ID Register, EL1 r0p4
Main ID Register
CPU Interface Identification Register
Peripheral Identification Register 2
Peripheral Identification Register 2
Peripheral Identification Register 2
ID Register 1
Peripheral Identification Register 2
Peripheral Identification Register 2
Added L2ACTLR_EL1.L2DEIEN bit description Auxiliary Control Register, EL1 r0p4
Added L2ACTLR_EL1.L2TEIEN bit description Auxiliary Control Register, EL1 r0p4
Added CPUACTLR_EL1.L1DEIEN bit description CPU Auxiliary Control Register, EL1 r0p4
Updated the reset value description for CPUACTLR_EL1.DTAH Table 4.124 r0p4
Added L2ACTLR.L2DEIEN bit description Auxiliary Control Register r0p4
Added L2ACTLR.L2TEIEN bit description Auxiliary Control Register r0p4
Added CPUACTLR.L1DEIEN bit description CPU Auxiliary Control Register r0p4
Updated the reset value description for CPUACTLR.DTAH Table 4.254 r0p4
Added section to describe error injection Error injection r0p4

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