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Clock and configuration signals

Table A.28 shows the clock and configuration signals for the ACP interface.

Table A.28. Clock and Configuration signals
Signal Direction Description
ACLKENS Input AXI slave bus clock enable.
AINACTS Input

ACP master is inactive and is not participating in coherency. There must be no outstanding transactions when the master asserts this signal, and while it is asserted the master must not send any new transactions:

0

ACP Master is active.

1

ACP Master is inactive.

Note

This signal must be asserted before the processor enters the low power L2 WFI state.


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