You copied the Doc URL to your clipboard.

Generic Interrupt Controller signals

Table A.4 shows the Generic Interrupt Controller (GIC) signals.

Table A.4. GIC signals
Signal Direction Description
nFIQ[CN:0] Input

FIQ request. Active-LOW, level sensitive, asynchronous FIQ interrupt request:

0

Activate FIQ interrupt.

1

Do not activate FIQ interrupt.

The processor treats the nFIQ input as level-sensitive. The nFIQ input must be asserted until the processor acknowledges the interrupt.

nIRQ[CN:0] Input

IRQ request input lines. Active-LOW, level sensitive, asynchronous interrupt request:

0

Activate interrupt.

1

Do not activate interrupt.

The processor treats the nIRQ input as level-sensitive. The nIRQ input must be asserted until the processor acknowledges the interrupt.

nSEI[CN:0] Input

System Error Interrupt request. Active-LOW, edge sensitive:

0

Activate SEI request.

1

Do not activate SEI request.

Asserting the nSEI input causes one of the following to occur:

  • Asynchronous Data Abort, if taken to AArch32. The DFSR.FS field is set to indicate an Asynchronous External Abort.

  • SError interrupt, if taken to AArch64. The ESR_ELx.ISS field is set, see Table 4.95.

nVFIQ[CN:0] Input

Virtual FIQ request. Active-LOW, level sensitive, asynchronous FIQ interrupt request:

0

Activate FIQ interrupt.

1

Do not activate FIQ interrupt.

The processor treats the nVFIQ input as level-sensitive. The nVFIQ input must be asserted until the processor acknowledges the interrupt. If the GIC is enabled by tying the GICCDISABLE input pin LOW, the nVFIQ input pin must be tied off to HIGH. If the GIC is disabled by tying the GICCDISABLE input pin HIGH, the nVFIQ input pin can be driven by an external GIC in the SoC.

nVIRQ[CN:0] Input

Virtual IRQ request. Active-LOW, level sensitive, asynchronous interrupt request:

0

Activate interrupt.

1

Do not activate interrupt.

The processor treats the nVIRQ input as level-sensitive. The nVIRQ input must be asserted until the processor acknowledges the interrupt. If the GIC is enabled by tying the GICCDISABLE input pin LOW, the nVIRQ input pin must be tied off to HIGH. If the GIC is disabled by tying the GICCDISABLE input pin HIGH, the nVIRQ input pin can be driven by an external GIC in the SoC.

nVSEI[CN:0] Input

Virtual System Error Interrupt request. Active-LOW, edge sensitive:

0

Activate virtual SEI request.

1

Do not activate virtual SEI request.

Asserting the nVSEI input causes one of the following to occur:

  • Asynchronous Data Abort, if taken to AArch32. The DFSR.FS field is set to indicate an Asynchronous External Abort.

  • SError interrupt, if taken to AArch64. The ESR_EL1.ISS field is set, see Table 4.95.

nREI[CN:0] Input

RAM Error Interrupt request. Active-LOW, edge sensitive:

0

Activate REI request. Reports an asynchronous RAM error in the system.

1

Do not activate REI request.

Asserting the nREI input causes one of the following to occur:

  • Asynchronous Data Abort, if taken to AArch32. The DFSR.FS field is set to indicate an Asynchronous parity error on memory access.

  • SError interrupt, if taken to AArch64. The ESR_ELx.ISS field is set, see Table 4.95.

nVCPUMNTIRQ[CN:0] Output Virtual CPU interface maintenance interrupt PPI output.
PERIPHBASE[39:18] Input

Specifies the base address for the GIC registers. This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset.

GICCDISABLE Input

Globally disables the GIC CPU interface logic and routes the “External” signals directly to the processor:

0

Enable the GIC CPU interface logic.

1

Disable the GIC CPU interface logic and route the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ signals directly to the processor. Drive this signal HIGH when using a legacy interrupt controller such as GIC-400 which does not support GICv3 or GICv4.

ICDTVALID Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TVALID indicates that the master is driving a valid transfer.
ICDTREADY Output AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TREADY indicates that the slave can accept a transfer in the current cycle.
ICDTDATA[15:0] Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TDATA is the primary payload that is used to provide the data that is passing across the interface.
ICDTLAST Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TLAST indicates the boundary of a packet.
ICDTDEST[1:0] Input AXI4 Stream Protocol signal. Distributor to GIC CPU Interface messages. TDEST provides routing information for the data stream.
ICCTVALID Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TVALID indicates that the master is driving a valid transfer.
ICCTREADY Input AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TREADY indicates that the slave can accept a transfer in the current cycle.
ICCTDATA[15:0] Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TDATA is the primary payload that is used to provide the data that is passing across the interface
ICCTLAST Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor messages. TLAST indicates the boundary of a packet.
ICCTID[1:0] Output AXI4 Stream Protocol signal. GIC CPU Interface to Distributor. TID is the data stream identifier that indicates different streams of data.

Was this page helpful? Yes No