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Power management signals

Table A.6 shows the non-Retention power management signals.

Table A.6. Non-Retention power management signals
Signal Direction Description
CLREXMONREQ Input

Clearing of the external global exclusive monitor request. When this signal is asserted, it acts as a WFE wake-up event to all the cores in the MPCore device. See CLREXMON request and acknowledge signaling for more information.

CLREXMONACK Output

Clearing of the external global exclusive monitor acknowledge. See CLREXMON request and acknowledge signaling for more information.

EVENTI Input Event input for processor wake-up from WFE state. See Event communication using WFE or SEV for more information.
EVENTO Output Event output. Active when a SEV instruction is executed. See Event communication using WFE or SEV for more information.
STANDBYWFI[CN:0] Output

Indicates whether a core is in WFI low-power state:

0

Core not in WFI low-power state.

1

Core in WFI low-power state. This is the reset condition.

STANDBYWFE[CN:0] Output

Indicates whether a core is in WFE low-power state:

0

Core not in WFE low-power state.

1

Core in WFE low-power state.

STANDBYWFIL2 Output

Indicates whether the L2 memory system is in WFI low-power state. This signal is active when the following conditions are met:

  • All cores are in WFI low-power state, held in reset, or nL2RESET is asserted LOW.

  • In an ACE configuration, ACINACTM is asserted HIGH.

  • In a CHI configuration, SINACT is asserted HIGH.

  • If ACP has been configured, AINACTS is asserted HIGH.

  • L2 memory system is idle.

L2FLUSHREQ Input L2 hardware flush request.
L2FLUSHDONE Output L2 hardware flush complete.
SMPEN[CN:0] Output Indicates whether a core is taking part in coherency.
DBGNOPWRDWN[CN:0] Output

Core no powerdown request

0

Do not request that the core stays powered up.

1

Request that the core stays powered up.

DBGPWRUPREQ[CN:0] Output

Core power up request:

0

Do not request that the core is powered up.

1

Request that the core is powered up.

DBGPWRDUP[CN:0] Input

Core powered up

0

Core is powered down.

1

Core is powered up.


Table A.7 shows the Retention power management signals.

Table A.7. Retention power management signals
Signal Direction Description
CPUQACTIVE[CN:0] Output Indicates whether the referenced core is active
CPUQREQn[CN:0] Input Indicates that the power controller is ready to enter or exit retention for the referenced core
CPUQDENY[CN:0] Output Indicates that the referenced core denies the power controller retention request
CPUQACCEPTn[CN:0] Output Indicates that the referenced core accepts the power controller retention request
NEONQACTIVE[CN:0] Output Indicates whether the referenced Advanced SIMD and Floating-point block is active
NEONQREQn[CN:0] Input Indicates that the power controller is ready to enter or exit retention for the referenced Advanced SIMD and Floating-point block
NEONQDENY[CN:0] Output Indicates that the referenced Advanced SIMD and Floating-point block denies the power controller retention request
NEONQACCEPTn[CN:0] Output Indicates that the referenced Advanced SIMD and Floating-point block accepts the power controller retention request
L2QACTIVE Output Indicates whether the L2 data RAMs are active
L2QREQn Input Indicates that the power controller is ready to enter or exit retention for the L2 data RAMs
L2QDENY Output Indicates that the L2 data RAMs deny the power controller retention request
L2QACCEPTn Output Indicates that the L2 data RAMs accept the power controller retention request

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