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Auxiliary Control Register

The ACTLR characteristics are:

Purpose

Controls write access to implementation defined registers in EL2, such as CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR and L2ACTLR.

Usage constraints

This register is accessible as follows:

EL0

NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW
Configurations

The processor does not implement the ACTLR (NS) register. This register is always res0. It is mapped to AArch64 register ACTLR_EL1. See Auxiliary Control Register, EL1.

ACTLR (S) is mapped to AArch64 register ACTLR_EL3. See Auxiliary Control Register, EL3.

Attributes

ACTLR is a 32-bit register.

Figure 4.99 shows the ACTLR bit assignments.

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Table 4.204 shows the ACTLR bit assignments.

Table 4.204.  ACTLR bit assignments
Bits Name Function
[31:7] -

Reserved, res0.

[6] L2ACTLR access control

L2ACTLR write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.

[5] L2ECTLR access control

L2ECTLR write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.

[4] L2CTLR access control

L2CTLR write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.

[3:2] - Reserved, res0.
[1] CPUECTLR access control

CPUECTLR write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.

[0] CPUACTLR access control

CPUACTLR write access control. The possible values are:

0

The register is not write accessible from a lower exception level. This is the reset value.

1

The register is write accessible from EL2.


To access the ACTLR:

	
MRC p15, 0, <Rt>, c1, c0, 1 ; Read ACTLR into Rt
MCR p15, 0, <Rt>, c1, c0, 1 ; Write Rt to ACTLR
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