The CLIDR characteristics are:
The type of cache, or caches, implemented at each level.
The Level of Coherency and Level of Unification for the cache hierarchy.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
CLIDR is architecturally mapped to AArch64 register CLIDR_EL1. See Cache Level ID Register.
There is one copy of this register that is used in both Secure and Non-secure states.
CLIDR is a 32-bit register.
Figure 4.93 shows the CLIDR bit assignments.
Table 4.193 shows the CLIDR bit assignments.
Indicates the Level of Unification Uniprocessor for the cache hierarchy:
Indicates the Level of Coherency for the cache hierarchy:
Indicates the Level of Unification Inner Shareable for the cache hierarchy:
Indicates the type of cache if the processor implements L3 cache:
Indicates the type of cache if the processor implements L2 cache:
Indicates the type of cache implemented at L1:
[a] If software reads the
Cache Type fields from Ctype1 upwards, after it has seen a value
To access the CLIDR:
MRC p15,1,<Rt>,c0,c0,1 ; Read CLIDR into Rt
Register access is encoded as follows: