Cache Size ID Register
The CCSIDR characteristics are:
- Purpose
-
Provides information about the architecture of the caches.
- Usage constraints
-
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2 EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO If CSSELR indicates a cache that is not implemented, then on a read of the CCSIDR the behavior is constrained unpredictable, and can be one of the following:
-
The CCSIDR read is treated as
NOP
. -
The CCSIDR read is undefined.
-
The CCSIDR read returns an unknown value (preferred).
-
- Configurations
-
CCSIDR is architecturally mapped to AArch64 register CCSIDR_EL1. See Cache Size ID Register.
There is one copy of this register that is used in both Secure and Non-secure states.
The implementation includes one CCSIDR for each cache that it can access. CSSELR selects which Cache Size ID Register is accessible.
- Attributes
-
CCSIDR is a 32-bit register.
Figure 4.92 shows the CCSIDR bit assignments.
Table 4.190 shows the CCSIDR bit assignments.
Bits | Name | Function |
---|---|---|
[31] | WT |
Indicates support for Write-Through:
|
[30] | WB |
Indicates support for Write-Back:
|
[29] | RA |
Indicates support for Read-Allocation:
|
[28] | WA |
Indicates support for Write-Allocation:
|
[27:13] | NumSets[a] |
Indicates the number of sets in cache - 1. Therefore, a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. |
[12:3] | Associativity[a] |
Indicates the associativity of cache - 1. Therefore, a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. |
[2:0] | LineSize[a] |
Indicates the (log2 (number of words in cache line)) - 2:
|
[a] For more information about encoding, see Table 4.191. |
Table 4.191 shows the individual bit field and complete register encodings for the CCSIDR. The CSSELR determines which CCSIDR to select.
CSSELR | Cache | Size | Complete register encoding | Register bit field encoding | ||||||
---|---|---|---|---|---|---|---|---|---|---|
WT | WB | RA | WA | NumSets | Associativity | LineSize | ||||
0x0 |
L1 Data cache | 8KB | 0x7003E01A |
0 | 1 | 1 | 1 | 0x001F |
0x003 |
0x2 |
16KB | 0x7007E01A |
0x003F |
0x003 |
0x2 |
||||||
32KB | 0x700FE01A |
0x007F |
0x003 |
0x2 |
||||||
64KB | 0x701FE01A |
0x00FF |
0x003 |
0x2 |
||||||
0x1 |
L1 Instruction cache | 8KB | 0x2007E00A |
0 | 0 | 1 | 0 | 0x003F |
0x001 |
0x2 |
16KB | 0x200FE00A |
0x007F |
0x001 |
0x2 |
||||||
32KB | 0x201FE00A |
0x00FF |
0x001 |
0x2 |
||||||
64KB | 0x203FE00A |
0x001F |
0x001 |
0x2 |
||||||
0x2 |
L2 cache | 128KB | 0x700FE07A |
0 | 1 | 1 | 1 | 0x007F |
0x00F |
0x2 |
256KB | 0x701FE07A |
0x00FF |
0x00F |
0x2 |
||||||
512KB | 0x703FE07A |
0x01FF |
0x00F |
0x2 |
||||||
1024KB | 0x707FE07A |
0x03FF |
0x00F |
0x2 |
||||||
2048KB | 0x70FFE07A |
0x07FF |
0x00F |
0x2 |
||||||
0x3-0xF |
Reserved | - | - | - | - | - | - | - | - | - |
To access the CCSIDR:
MRC p15, 1, <Rt>, c0, c0, 0 ; Read CCSIDR into Rt
Register access is encoded as follows: