The CSSELR characteristics are:
Selects the current CCSIDR, see Cache Size ID Register, by specifying:
The required cache level.
The cache type, either instruction or data cache.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RW RW RW RW RW
If the CSSELR level field is programmed to a cache level that is not implemented, then a read of CSSELR returns an unknown value in CSSELR.Level.
CSSELR (NS) is architecturally mapped to AArch64 register CSSELR_EL1. See Cache Size Selection Register.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
CSSELR is a 32-bit register.
Figure 4.94 shows the CSSELR bit assignments.
Table 4.195 shows the CSSELR bit assignments.
Cache level of required cache:
Instruction not Data bit:
[a] The combination
To access the CSSELR:
MRC p15, 2, <Rt>, c0, c0, 0; Read CSSELR into Rt MCR p15, 2, <Rt>, c0, c0, 0; Write Rt to CSSELR
Register access is encoded as follows: