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CPU Extended Control Register

The CPUECTLR characteristics are:

Purpose

Provides additional implementation defined configuration and control options for the processor.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

The CPUECTLR can be written dynamically.

Configurations

The CPUECTLR is:

Attributes

CPUECTLR is a 64-bit register.

Figure 4.141 shows the CPUECTLR bit assignments.

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Table 4.255 shows the CPUECTLR bit assignments.

Table 4.255. CPUECTLR bit assignments
Bits Name Function
[63:7] -

Reserved, res0.

[6]

SMPEN

Enable hardware management of data coherency with other cores in the cluster. The possible values are:

0

Disables data coherency with other cores in the cluster. This is the reset value.

1

Enables data coherency with other cores in the cluster.

Note

Set the SMPEN bit before enabling the caches, even if there is only one core in the system.

[5:3] FPRETCTL

Advanced SIMD and Floating-point retention control. The possible values are:

0b000

Disable the retention circuit. This is the reset value.

0b001

2 Architectural Timer ticks are required before retention entry.

0b010

8 Architectural Timer ticks are required before retention entry.

0b011

32 Architectural Timer ticks are required before retention entry.

0b100

64 Architectural Timer ticks are required before retention entry.

0b101

128 Architectural Timer ticks are required before retention entry.

0b110

256 Architectural Timer ticks are required before retention entry.

0b111

512 Architectural Timer ticks are required before retention entry.

Note

This field is present only if the Advanced SIMD and Floating-point Extension is implemented. Otherwise, it is res0.

[2:0] CPURETCTL

CPU retention control. The possible values are:

0b000

Disable the retention circuit. This is the reset value.

0b001

2 Architectural Timer ticks are required before retention entry.

0b010

8 Architectural Timer ticks are required before retention entry.

0b011

32 Architectural Timer ticks are required before retention entry.

0b100

64 Architectural Timer ticks are required before retention entry.

0b101

128 Architectural Timer ticks are required before retention entry.

0b110

256 Architectural Timer ticks are required before retention entry.

0b111

512 Architectural Timer ticks are required before retention entry.


To access the CPUECTLR:

	
MRRC p15, 1, <Rt>, <Rt2>, c15; Read CPU Extended Control Register
MCRR p15, 1, <Rt>, <Rt2>, c15; Write CPU Extended Control Register
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