The DACR characteristics are:
Defines the access permission for each of the sixteen memory domains.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RW RW RW RW RW
DACR (NS) is architecturally mapped to AArch64 register DACR32_EL2. See Domain Access Control Register.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
DACR has write access to the Secure instance of the register disabled when the CP15SDISABLE signal is asserted HIGH.
DACR has no function when TTBCR.EAE is set to 1, to select the Long-descriptor translation table format.
DACR is a 32-bit register.
Figure 4.119 shows the DACR bit assignments.
Table 4.224 shows the DACR bit assignments.
D<n>, bits [2n+1:2n], for n = 0 to 15
Domain n access permission, where n = 0 to 15. Permitted values are:
To access the DACR:
MRC p15, 0, <Rt>, c3, c0, 0 ; Read DACR into Rt MCR p15, 0, <Rt>, c3, c0, 0 ; Write Rt to DACR