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Hyp Auxiliary Control Register

The HACTLR characteristics are:

Purpose

Controls write access to implementation defined registers in Non-secure EL1 modes, such as CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR and L2ACTLR.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -
Configurations

The HACTLR is architecturally mapped to the AArch4 ACTLR_EL2 register. See Auxiliary Control Register, EL2.

Attributes

HACTLR is a 32-bit register.

Figure 4.105 shows the HACTLR bit assignments.

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Table 4.210 shows the HACTLR bit assignments.

Table 4.210. HACTLR bit assignments
Bits Name Function
[31:7] -

Reserved, res0.

[6] L2ACTLR access control

L2ACTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[6] to be set.

[5] L2ECTLR access control

L2ECTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[5] to be set.

[4] L2CTLR access control

L2CTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[4] to be set.

[3:2] -

Reserved, res0.

[1] CPUECTLR access control

CPUECTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[1] to be set.

[0] CPUACTLR access control

CPUACTLR write access control. The possible values are:

0

The register is not write accessible from Non-secure EL1.

This is the reset value.

1

The register is write accessible from Non-secure EL1.

Write access from Non-secure EL1 also requires ACTLR(S)[0] to be set.


To access the HACTLR:

	
MRC p15,4,<Rt>,c1,c0,1 ; Read HACTLR into Rt
MCR p15,4,<Rt>,c1,c0,1 ; Write Rt to HACTLR
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