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Hyp Configuration Register

The HCR characteristics are:

Purpose

Provides configuration controls for virtualization, including defining whether various Non-secure operations are trapped to Hyp mode.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

  - - - RW RW -
Configurations

HCR is architecturally mapped to AArch64 register HCR_EL2[31:0]. See Hypervisor Configuration Register.

Attributes

HCR is a 32-bit register.

Figure 4.107 shows the HCR bit assignments.

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Table 4.212 shows the HCR bit assignments.

Table 4.212. HCR bit assignments
Bits Name Function
[31] -

Reserved, res0.

[30] TRVM

Trap Read of Virtual Memory controls.

When 1, this causes Reads to the EL1 virtual memory control registers from EL1 to be trapped to EL2. This covers the following registers:

SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR, PRRR/MAIR0, NMRR/MAIR1, AMAIR0, AMAIR1, and CONTEXTIDR.

The reset value is 0.

[29] HCD

Hyp Call Disable. The HCD value is:

0

HVC is enabled at EL1 or EL2.

1

HVC is undefined at all exception levels.

[28] - Reserved, res0.
[27] TGE

Trap General Exceptions. If this bit is set, and SCR_EL3.NS is set, then:

All exceptions that would be routed to EL1 are routed to EL2.

  • The SCTLR.M bit is treated as 0 regardless of its actual state, other than for the purpose of reading the bit.

  • The HCR.FMO, IMO, and AMO bits are treated as 1 regardless of their actual state, other than for the purpose of reading the bits.

  • All virtual interrupts are disabled.

  • Any implementation defined mechanisms for signaling virtual interrupts are disabled.

  • An exception return to EL1 is treated as an illegal exception return.

Additionally, if HCR.TGE is 1, the HDCR.{TDRA,TDOSA,TDA} bits are ignored and the processor behaves as if they are set to 1, other than for the value read back from HDCR.

The reset value is 0.

[26] TVM

Trap Virtual Memory controls. When 1, this causes Writes to the EL1 virtual memory control registers from EL1 to be trapped to EL2. This covers the following registers:

SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR, PRRR/MAIR0, NMRR/MAIR1, AMAIR0, AMAIR1, and CONTEXTIDR.

The reset value is 0.

[25] TTLB

Trap TLB maintenance instructions. When 1, this causes TLB maintenance instructions executed from EL1 that are not undefined to be trapped to EL2. This covers the following instructions:

TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIALL, TLBIMVA, TLBIASID, TLBIMVAA, TLBIMVALIS, TLBIMVAALIS, TLBIMVAL, and TLBIMVAAL.

The reset value is 0.

[24] TPU

Trap Cache maintenance instructions to Point of Unification. When 1, this causes Cache maintenance instructions to the point of unification executed from EL1 or EL0 that are not undefined to be trapped to EL2. This covers the following instructions:

ICIMVAU, ICIALLU, ICIALLUIS, and DCCMVAU.

The reset value is 0.

[23] TPC

Trap Data/Unified Cache maintenance operations to Point of Coherency. When 1, this causes Data or Unified Cache maintenance instructions by address to the point of coherency executed from EL1 or EL0 that are not undefined to be trapped to EL2. This covers the following instructions:

DCIMVAC, DCCIMVAC, and DCCMVAC.

The reset value is 0.

[22] TSW

Trap Data/Unified Cache maintenance operations by Set/Way. When 1, this causes Data or Unified Cache maintenance instructions by set/way executed from EL1 that are not undefined to be trapped to EL2. This covers the following instructions:

DCISW, DCCSW, and DCCISW.

The reset value is 0.

[21] TAC

Trap ACTLR accesses. When this bit is set to 1, any valid Non-secure access to the ACTLR is trapped to Hyp mode.

The reset value is 0.

[20] TIDCP

Trap Implementation Dependent functionality. When 1, this causes accesses to all CP15 MCR and MRC instructions executed from EL1, to be trapped to EL2 as follows:

  • CRn is 9, Opcode1 is 0 to 7, CRm is c0, c1, c2, c5, c6, c7, c8, opcode2 is 0 to 7.

  • CRn is 10, Opcode1 is 0 to 7, CRm is c0, c1, c4, c8}, opcode2 is 0 to 7.

  • CRn is 11, Opcode1 is 0 to 7, CRm is c0 to c8, or c15, opcode2 is 0 to 7.

Accesses from EL0 are undefined.

Resets to 0.

[19] TSC

Trap SMC instruction. When this bit is set to 1, any attempt from a Non-secure EL1 state to execute an SMC instruction, that passes its condition check if it is conditional, is trapped to Hyp mode.

The reset value is 0.

[18] TID3

Trap ID Group 3. When 1, this causes reads to the following registers executed from EL1 to be trapped to EL2:

ID_PFR0, ID_PFR1, ID_DFR0, ID_AFR0, ID_MMFR0, ID_MMFR1, ID_MMFR2, ID_MMFR3, ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, ID_ISAR5, MVFR0, MVFR1, and MVFR2. Also MRC instructions to any of the following encodings:

  • CP15, OPC1 is 0, CRn is 0, CRm is c3, c4, c5, c6, or c7, and Opc2 is 0 or 1.

  • CP15, Opc1 is 0, CRn is 0, CRm is c3, and Opc2 is 2.

  • CP15, Opc1 is 0, CRn is 0, CRm is 5, and Opc2 is 4 or 5.

The reset value is 0.

[17] TID2

Trap ID Group 2. When 1, this causes reads (or writes to CSSELR) to the following registers executed from EL1 or EL0 if not undefined to be trapped to EL2:

CTR, CCSIDR, CLIDR, and CSSELR.

The reset value is 0.

[16] TID1

Trap ID Group 1. When 1, this causes reads to the following registers executed from EL1 to be trapped to EL2:

TCMTR, TLBTR, AIDR, and REVIDR.

The reset value is 0.

[15] TID0

Trap ID Group 0. When 1, this causes reads to the following registers executed from EL1 or EL0 if not undefined to be trapped to EL2:

FPSID and JIDR.

The reset value is 0.

[14] TWE

Trap WFE. When 1, this causes the WFE instruction executed from EL1 or EL0 to be trapped to EL2 if the instruction would otherwise cause suspension of execution. For example, if the event register is not set:

The reset value is 0.

[13] TWI

Trap WFI. When 1, this causes the WFI instruction executed from EL1 or EL0 to be trapped to EL2 if the instruction would otherwise cause suspension of execution. For example, if there is not a pending WFI wake-up event:

The reset value is 0.

[12] DC

Default cacheable. When this bit is set to 1, and the Non-secure EL1 and EL0 stage 1 MMU is disabled, the memory type and attributes determined by the stage 1 translation is Normal, Non-shareable, Inner Write-Back Write-Allocate, Outer Write-Back Write-Allocate.

The reset value is 0.

[11:10] BSU

Barrier Shareability upgrade. The value in this field determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0. The possible values are:

0b00

No effect.

0b01

Inner Shareable.

0b10

Outer Shareable.

0b11

Full System.

The reset value is 0.

[9] FB

Force broadcast. When 1, this causes the following instructions to be broadcast within the Inner Shareable domain when executed from Non-secure EL1:

TLBIALL, TLBIMVA, TLBIASID, TLBIMVAA, BPIALL, and ICIALLU.

The reset value is 0.

[8] VA

Virtual Asynchronous Abort exception. When the AMO bit is set to 1, setting this bit signals a virtual Asynchronous Abort exception to the Guest OS, when the processor is executing in Non-secure state at EL0 or EL1.

The Guest OS cannot distinguish the virtual exception from the corresponding physical exception.

The reset value is 0.

[7] VI

Virtual IRQ exception. When the IMO bit is set to 1, setting this bit signals a virtual IRQ exception to the Guest OS, when the processor is executing in Non-secure state at EL0 or EL1.

The Guest OS cannot distinguish the virtual exception from the corresponding physical exception.

The reset value is 0.

[6] VF

Virtual FIQ exception. When the FMO bit is set to 1, setting this bit signals a virtual FIQ exception to the Guest OS, when the processor is executing in Non-secure state at EL0 or EL1.

The Guest OS cannot distinguish the virtual exception from the corresponding physical exception.

The reset value is 0.

[5] AMO

Asynchronous Abort Mask Override. When this is set to 1, it overrides the effect of CPSR.A, and enables virtual exception signaling by the VA bit.

The reset value is 0.

[4] IMO

IRQ Mask Override. When this is set to 1, it overrides the effect of CPSR.I, and enables virtual exception signaling by the VI bit.

The reset value is 0.

[3] FMO

FIQ Mask Override. When this is set to 1, it overrides the effect of CPSR.F, and enables virtual exception signaling by the VF bit.

The reset value is 0.

[2] PTW

Protected Table Walk. When 1, if the stage 2 translation of a translation table access made as part of a stage 1 translation table walk at EL0 or EL1 maps that translation table access to Device memory, the access is faulted as a stage 2 Permission fault.

The reset value is 0.

[1] SWIO

Set/Way Invalidation Override. When 1, this causes EL1 execution of the data cache invalidate by set/way instruction to be treated as data cache clean and invalidate by set/way. DCISW is executed as DCCISW.

This bit is res1.

[0] VM

Second stage of Translation enable. When 1, this enables the second stage of translation for execution in EL1 and EL0.

The reset value is 0.


To access the HCR:

	
MRC p15, 4, <Rt>, c1, c1, 0; Read Hyp Configuration Register
MCR p15, 4, <Rt>, c1, c1, 0; Write Hyp Configuration Register
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