The HDFAR characteristics are:
Holds the virtual address of the faulting address that caused a synchronous Data Abort exception that is taken to Hyp mode.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
- - - RW RW -
An execution in a Non-secure EL1 state, or in Secure state, makes the HDFAR unknown.
HDFAR is architecturally mapped to AArch64 register FAR_EL2[31:0] when EL3 is AArch64. See Fault Address Register, EL2.
HDFAR (S) is architecturally mapped to AArch32 register DFAR (S). See Data Fault Address Register.
HDFAR is a 32-bit register.
Figure 4.128 shows the HDFAR bit assignments.
Table 4.236 shows the HDFAR bit assignments.
The Virtual Address of faulting address of synchronous Data Abort exception
To access the HDFAR:
MRC p15, 4, <Rt>, c6, c0, 0 ; Read HDFAR into Rt MCR p15, 4, <Rt>, c6, c0, 0 ; Write Rt to HDFAR