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Hyp Debug Control Register

The HDCR characteristics are:

Purpose

Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to functions provided by the debug and trace architectures and the Performance Monitor.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -
Configurations
  • HDCR is architecturally mapped to AArch64 register MDCR_EL2. See Hyp Debug Control Register .

  • This register is accessible only at EL2 or EL3.

Attributes

HDCR is a 32-bit register.

Figure 4.109 shows the HDCR bit assignments.

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Table 4.214 shows the HDCR bit assignments.

Table 4.214. HDCR bit assignments
Bits Name Function
[31:12] -

Reserved, res0.

[11] TDRA

Trap debug ROM address register access.

0

Has no effect on accesses to debug ROM address registers from EL1 and EL0.

1

Trap valid Non-secure EL1 and EL0 access to debug ROM address registers to Hyp mode.

When this bit is set to 1, any valid Non-secure access to the following registers is trapped to Hyp mode:

  • DBGDRAR.

  • DBGDSAR.

If HCR.TGE is 1 or HDCR.TDE is 1, then this bit is ignored and treated as though it is 1 other than for the value read back from HDCR.

On Warm reset, the field resets to 0.

[10] TDOSA

Trap Debug OS-related register access:

0

Has no effect on accesses to CP14 Debug registers.

1

Trap valid Non-secure accesses to CP14 OS-related Debug registers to Hyp mode.

When this bit is set to 1, any valid Non-secure CP14 access to the following OS-related Debug registers is trapped to Hyp mode:

  • DBGOSLSR.

  • DBGOSLAR.

  • DBGOSDLR.

  • DBGPRCR.

If HCR.TGE is 1 or HDCR.TDE is 1, then this bit is ignored and treated as though it is 1 other than for the value read back from HDCR.

On Warm reset, the field resets to 0.

[9] TDA

Trap Debug Access:

0

Has no effect on accesses to CP14 Debug registers.

1

Trap valid Non-secure accesses to CP14 Debug registers to Hyp mode.

When this bit is set to 1, any valid access to the CP14 Debug registers, other than the registers trapped by the TDRA and TDOSA bits, is trapped to Hyp mode.

If HCR.TGE is 1 or HDCR.TDE is1, then this bit is ignored and treated as though it is 1 other than for the value read back from HDCR.

On Warm reset, the field resets to 0.

[8] TDE

Trap Debug Exceptions:

0

Has no effect on Debug exceptions.

1

Route Non-secure Debug exceptions to Hyp mode.

When this bit is set to 1, any Debug exception taken in Non-secure state is trapped to Hyp mode.

If HCR.TGE is 1, then this bit is ignored and treated as though it is 1 other than for the value read back from HDCR.This bit resets to 0.

[7] HPME

Hypervisor Performance Monitor Enable:

0

Hyp mode performance monitor counters disabled.

1

Hyp mode performance monitor counters enabled.

When this bit is set to 1, access to the performance monitors that are reserved for use from Hyp mode is enabled. For more information, see the description of the HPMN field.

The reset value of this bit is unknown.

[6] TPM

Trap Performance Monitor accesses:

0

Has no effect on performance monitor accesses.

1

Trap valid Non-secure performance monitor accesses to Hyp mode.

When this bit is set to 1, any valid Non-secure access to the Performance Monitor registers is trapped to Hyp mode. This bit resets to 0. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

[5] TPMCR

Trap Performance Monitor Control Register accesses:

0

Has no effect on PMCR accesses.

1

Trap valid Non-secure PMCR accesses to Hyp mode.

When this bit is set to 1, any valid Non-secure access to the PMCR is trapped to Hyp mode. This bit resets to 0. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

[4:0] HPMN

Hyp Performance Monitor count. Defines the number of Performance Monitors counters that are accessible from Non-secure EL1 and EL0 modes if unprivileged access is enabled.

In Non-secure state, HPMN divides the Performance Monitors counters as follows. If software is accessing Performance Monitors counter n then, in Non-secure state:

For example, If PMnEVCNTR is performance monitor counter n then, in Non-secure state:

  • If n is in the range 0 ≤ n < HPMN, the counter is accessible from EL1 and EL2, and from EL0 if unprivileged access to the counters is enabled.

  • If n is in the range HPMN ≤ n <PMCR.N, the counter is accessible only from EL2. The HPME bit enables access to the counters in this range.

If this field is set to 0, or to a value larger than PMCR.N, then the behavior in Non-secure EL0 and EL1 is constrained unpredictable, and one of the following must happen:

  • The number of counters accessible is an unknown non-zero value less than PMCR.N.

  • There is no access to any counters.

For reads of HDCR.HPMN by EL2 or higher, if this field is set to 0 or to a value larger than PMCR.N, the processor must return a constrained unpredictable value being one of:

  • PMCR.N.

  • The value that was written to HDCR.HPMN.

  • (The value that was written to HDCR.HPMN) modulo 2h, where h is the smallest number of bits required for a value in the range 0 to PMCR.N.

This field resets to 0x6.


To access the HDCR:

	
MRC p15,4,<Rt>,c1,c1,1 ; Read HDCR into Rt
MCR p15,4,<Rt>,c1,c1,1 ; Write Rt to HDCR
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