The HIFAR characteristics are:
Holds the virtual address of the faulting address that caused a synchronous Prefetch Abort exception that is taken to Hyp mode.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - - RW RW -
Execution in any Non-secure mode other than Hyp mode makes HPFAR unknown.
HIFAR is architecturally mapped to AArch64 register FAR_EL2[63:32]. See Fault Address Register, EL2.
HIFAR is architecturally mapped to AArch32 register IFAR (S). See Instruction Fault Address Register.
HIFAR is a 32-bit register.
Figure 4.129 shows the HIFAR bit assignments.
Table 4.237 shows the HIFAR bit assignments.
The Virtual Address of faulting address of synchronous Prefetch Abort exception
To access the HIFAR:
MRC p15, 4, <Rt>, c6, c0, 2 ; Read HIFAR into Rt MCR p15, 4, <Rt>, c6, c0, 2 ; Write Rt to HIFAR