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Hyp Instruction Fault Address Register

The HIFAR characteristics are:

Purpose

Holds the virtual address of the faulting address that caused a synchronous Prefetch Abort exception that is taken to Hyp mode.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -

Execution in any Non-secure mode other than Hyp mode makes HPFAR unknown.

Configurations

HIFAR is architecturally mapped to AArch64 register FAR_EL2[63:32]. See Fault Address Register, EL2.

HIFAR is architecturally mapped to AArch32 register IFAR (S). See Instruction Fault Address Register.

Attributes

HIFAR is a 32-bit register.

Figure 4.129 shows the HIFAR bit assignments.

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Table 4.237 shows the HIFAR bit assignments.

Table 4.237.  HIFAR bit assignments
Bits Name Function
[31:0] VA

The Virtual Address of faulting address of synchronous Prefetch Abort exception


To access the HIFAR:

	
MRC p15, 4, <Rt>, c6, c0, 2 ; Read HIFAR into Rt
MCR p15, 4, <Rt>, c6, c0, 2 ; Write Rt to HIFAR
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