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Hyp IPA Fault Address Register

The HPFAR characteristics are:

Purpose

Holds the faulting IPA for some aborts on a stage 2 translation taken to Hyp mode.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - - RW RW -

Execution in any Non-secure mode other than Hyp mode makes HPFAR unknown.

Configurations

HPFAR is architecturally mapped to AArch64 register HPFAR_EL2[31:0]. See Hypervisor IPA Fault Address Register, EL2.

Attributes

HPFAR is a 32-bit register.

Figure 4.130 shows the HPFAR bit assignments.

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Table 4.238 shows the HPFAR bit assignments.

Table 4.238.  HPFAR bit assignments
Bits Name Function
[31:4] FIPA[39:12]

Bits [39:12] of the faulting intermediate physical address

[3:0] - Reserved, res0

To access the HPFAR:

	
MRC p15, 4, <Rt>, c6, c0, 4 ; Read HPFAR into Rt
MCR p15, 4, <Rt>, c6, c0, 4 ; Write Rt to HPFAR
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