The IFAR characteristics are:
Holds the virtual address of the faulting address that caused a synchronous Prefetch Abort exception.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
IFAR(S) - - - RW - - RW IFAR(NS) - - RW - RW RW -
IFAR (NS) is architecturally mapped to AArch64 register FAR_EL1[63:32]. See Fault Address Register, EL1.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
IFAR (S) is architecturally mapped to AArch32 register HIFAR.
IFAR (S) is architecturally mapped to AArch64 register FAR_EL2[63:32]. See Fault Address Register, EL2.
IFAR is a 32-bit register.
Figure 4.127 shows the IFAR bit assignments.
Table 4.235 shows the IFAR bit assignments.
The Virtual Address of faulting address of synchronous Prefetch Abort exception
To access the IFAR:
MRC p15, 0, <Rt>, c6, c0, 2; Read IFAR into Rt MCR p15, 0, <Rt>, c6, c0, 2; Write Rt to IFAR