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Instruction Set Attribute Register 5

The ID_ISAR5 characteristics are:

Purpose

Provides information about the instruction sets that the processor implements.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO

ID_ISAR5 must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR4. See:

Configurations

ID_ISAR5 is architecturally mapped to AArch64 register ID_ISAR5_EL1. See AArch32 Instruction Set Attribute Register 5.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

ID_ISAR5 is a 32-bit register.

Figure 4.91 shows the ID_ISAR5 bit assignments.

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Table 4.188 shows the ID_ISAR5 bit assignments.

Table 4.188. ID_ISAR5 bit assignments
Bits Name Function
[31:20] -

Reserved, res0.

[19:16] CRC32

Indicates whether CRC32 instructions are implemented in AArch32 state:

0x1

CRC32 instructions are implemented.

[15:12] SHA2

Indicates whether SHA2 instructions are implemented in AArch32 state:

0x0

Cryptography Extensions are not implemented or are disabled.

0x1

SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions are implemented.

See the Cortex®-A53 MPCore Processor Cryptography Extension Technical Reference Manual for more information.

[11:8] SHA1

Indicates whether SHA1 instructions are implemented in AArch32 state:

0x0

Cryptography Extensions are not implemented or are disabled.

0x1

SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions are implemented.

See the Cortex®-A53 MPCore Processor Cryptography Extension Technical Reference Manual for more information.

[7:4] AES

Indicates whether AES instructions are implemented in AArch32 state:

0x0

Cryptography Extensions are not implemented or are disabled.

0x2

AESE, AESD, AESMC and AESIMC, plus PMULL and PMULL2 instructions operating on 64-bit data.

See the Cortex®-A53 MPCore Processor Cryptography Extension Technical Reference Manual for more information.

[3:0] SEVL

Indicates whether the SEVL instruction is implemented:

0x1

SEVL implemented to send event local.


To access the ID_ISAR5:

	
MRC p15,0,<Rt>,c0,c2,5 ; Read ID_ISAR5 into Rt

Register access is encoded as follows:

Table 4.189. ID_ISAR5 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 101

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