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Main ID Register

The MIDR characteristics are:

Purpose

Provides identification information for the processor, including an implementer code for the device and a device ID number.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO
Configurations

The MIDR is:

Attributes

MIDR is a 32-bit register.

Figure 4.76 shows the MIDR bit assignments.

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Table 4.158 shows the MIDR bit assignments.

Table 4.158. MIDR bit assignments
Bits Name Function
[31:24] Implementer

Indicates the implementer code. This value is:

0x41

ASCII character 'A' - implementer is ARM Limited.

[23:20] Variant

Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status. This value is:

0x0

r0p4.

[19:16] Architecture

Indicates the architecture code. This value is:

0xF

Defined by CPUID scheme.

[15:4] PartNum

Indicates the primary part number. This value is:

0xD03

Cortex-A53 processor.

[3:0] Revision

Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status. This value is:

0x4

r0p4.


To access the MIDR:

	
MRC p15, 0, <Rt>, c0, c0, 0; Read MIDR into Rt

Register access is encoded as follows:

Table 4.159. MPIDR access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0000 000

The MIDR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xD00.

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