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Memory Attribute Indirection Registers 0 and 1

The MAIR0 and MAIR1 characteristics are:

Purpose

To provide the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations.

Usage constraints

These registers are accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

Accessible only when using the Long-descriptor translation table format. When using the Short-descriptor format see, instead, Primary Region Remap Register and Normal Memory Remap Register.

AttrIndx[2], from the translation table descriptor, selects the appropriate MAIR: setting AttrIndx[2] to 0 selects MAIR0.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

The Secure instance of the register gives the value for memory accesses from Secure state.

The Non-secure instance of the register gives the value for memory accesses from Non-secure states other than Hyp mode.

Configurations

MAIR0 (NS) is architecturally mapped to AArch64 register MAIR_EL1[31:0] when TTBCR.EAE==1. See Memory Attribute Indirection Register, EL1.

MAIR0 (S) is mapped to AArch64 register MAIR_EL3[31:0] when TTBCR.EAE==1. See Memory Attribute Indirection Register, EL3.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

MAIR0 has write access to the Secure instance of the register disabled when the CP15SDISABLE signal is asserted HIGH.

Attributes

MAIR0 is a 32-bit register when TTBCR.EAE==1.

Figure 4.134 shows the MAIR0 and MAIR1 bit assignments.

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Table 4.243 shows the MAIR0 and MAIR1 bit assignments.

Table 4.243. MAIR0 and MAIR1 bit assignments
Bits Name Description
[7:0] Attrm[a]

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:

  • AttrIndx[2] selects the appropriate MAIR:

    • Setting AttrIndx[2] to 0 selects MAIR0.

    • Setting AttrIndx[2] to 1 selects MAIR1.

  • AttrIndx[2:0] gives the value of <n> in Attr<n>.

[a] Where m is 0-7.


Table 4.244 shows the Attr<n>[7:4] bit assignments.

Table 4.244. Attr<n>[7:4] bit assignments
Bits Meaning
0b0000 Device memory. See Table 4.245 for the type of Device memory.
0b00RW, RW not 00 Normal Memory, Outer Write-through transient.[a]
0b0100 Normal Memory, Outer Non-Cacheable.
0b01RW, RW not 00 Normal Memory, Outer Write-back transient.[a]
0b10RW Normal Memory, Outer Write-through non-transient.
0b11RW Normal Memory, Outer Write-back non-transient.

[a] The transient hint is ignored.


Table 4.245 shows the Attr<n>[3:0] bit assignments. The encoding of Attr<n>[3:0] depends on the value of Attr<n>[7:4], as Table 4.245 shows.

Table 4.245. Attr<n>[3:0] bit assignments
Bits Meaning when Attr<n>[7:4] is 0000 Meaning when Attr<n>[7:4] is not 0000
0b0000 Device-nGnRnE memory unpredictable
0b00RW, RW not 00 unpredictable Normal Memory, Inner Write-through transient
0b0100 Device-nGnRE memory Normal memory, Inner Non-Cacheable
0b01RW, RW not 00 unpredictable Normal Memory, Inner Write-back transient
0b1000 Device-nGRE memory Normal Memory, Inner Write-throughnon-transient (RW=00)
0b10RW, RW not 00 unpredictable Normal Memory, Inner Write-through non-transient
0b1100 Device-GRE memory Normal Memory, Inner Write-back non-transient (RW=00)
0b11RW, RW not 00 unpredictable Normal Memory, Inner Write-back non-transient

Table 4.246 shows the encoding of the R and W bits that are used, in some Attr<n> encodings in Table 4.244and Table 4.245, to define the read-allocate and write-allocate policies:

Table 4.246. Encoding of R and W bits in some Attrm fields
R or W Meaning
0 Do not allocate
1 Allocate

To access the MAIR0:

	
MRC p15, 0, <Rt>, c10, c2, 0    ; Read MAIR0 into Rt
MCR p15, 0, <Rt>, c10, c2, 0    ; Write Rt to MAIR0

To access the MAIR1:

	
MRC p15, 0, <Rt>, c10, c2, 1    ; Read MAIR1 into Rt
MCR p15, 0, <Rt>, c10, c2, 1    ; Write Rt to MAIR1
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