The ID_MMFR0 characteristics are:
Provides information about the memory model and memory management support in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_MMFR1, ID_MMFR2, and ID_MMFR3. See:
ID_MMFR0 is architecturally mapped to AArch64 register ID_MMFR0_EL1.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_MMFR0 is a 32-bit register.
Figure 4.82 shows the ID_MMFR0 bit assignments.
Table 4.170 shows the ID_MMFR0 bit assignments.
Indicates the innermost shareability domain implemented:
Indicates support for Fast Context Switch Extension (FCSE):
Indicates support for Auxiliary registers:
Indicates support for TCMs and associated DMAs:
Indicates the number of shareability levels implemented:
Indicates the outermost shareability domain implemented:
Indicates support for a Protected Memory System Architecture (PMSA):
Indicates support for a Virtual Memory System Architecture (VMSA).
To access the ID_MMFR0:
MRC p15,0,<Rt>,c0,c1,4 ; Read ID_MMFR0 into Rt
Register access is encoded as follows: