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Non-Secure Access Control Register

The NSACR characteristics are:

Purpose

Defines the Non-secure access permission to CP0 to CP13.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RW RW

Any read or write to NSACR in Secure EL1 state in AArch32 is trapped as an exception to EL3.

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

If EL3 is using AArch64, then any reads of the NSACR from Non-secure EL2 or Non-secure EL1 using AArch32 return a fixed value of 0x00000C00.

In AArch64, the NSACR functionality is replaced by the behavior in CPTR_EL3.

Attributes

NSACR is a 32-bit register.

Figure 4.103 shows the NSACR bit assignments.

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Table 4.208 shows the NSACR bit assignments.

Table 4.208. NSACR bit assignments
Bits Name Function
[31:16] -

Reserved, res0.

[15] NSASEDIS

Disable Non-secure Advanced SIMD functionality:

0

This bit has no effect on the ability to write CPACR.ASEDIS, this is the reset value.

1

When executing in Non-secure state, the CPACR.ASEDIS bit has a fixed value of 1 and writes to it are ignored.

If Advanced SIMD and Floating-point are not implemented, this bit is res0.

[14:12] -

Reserved, res0.

[11] cp11

Non-secure access to CP11 enable:

0

Secure access only. Any attempt to access CP11 in Non-secure state results in an Undefined Instruction exception. If the processor is in Non-secure state, the corresponding bits in the CPACR ignore writes and read as 0b00, access denied. This is the reset value.

1

Secure or Non-secure access.

If Advanced SIMD and Floating-point are not implemented, this bit is res0.

[10] cp10

Non-secure access to CP10 enable:

0

Secure access only. Any attempt to access CP10 in Non-secure state results in an Undefined Instruction exception. If the processor is in Non-secure state, the corresponding bits in the CPACR ignore writes and read as 0b00, access denied. This is the reset value.

1

Secure or Non-secure access.

If Advanced SIMD and Floating-point are not implemented, this bit is res0.

[9:0] -

Reserved, res0.


Note

If the CP11 and CP10 fields are set to different values, the behavior is CONSTRAINED UNPREDICTABLE. It is the same as if both fields were set to the value of CP10, in all respects other than the value read back by explicitly reading CP11.

To access the NSACR:

	
MRC p15, 0, <Rt>, c1, c1, 2 ; Read NSACR into Rt
MCR p15, 0, <Rt>, c1, c1, 2 ; Write Rt to NSACR
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