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Primary Region Remap Register

The PRRR characteristics are:

Purpose

Controls the top level mapping of the TEX[0], C, and B memory region attributes.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

PRRR is not accessible when the Long-descriptor translation table format is in use. See, instead, Memory Attribute Indirection Registers 0 and 1.

Configurations

PRRR (NS) is architecturally mapped to AArch64 register MAIR_EL1[31:0] when TTBCR.EAE is 0.

PRRR (S) is mapped to AArch64 register MAIR_EL3[31:0] when TTBCR.EAE is 0.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

PRRR has write access to the Secure instance of the register disabled when the CP15SDISABLE signal is asserted HIGH.

Attributes

PRRR is a 32-bit register when TTBCR.EAE==0.

Figure 4.133 shows the PRRR bit assignments.

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Table 4.241 shows the PRRR bit assignments.

Table 4.241. PRRR bit assignments
Bits Name Function
[24+n][a] NOSn

Outer Shareable property mapping for memory attributes n, if the region is mapped as Normal Shareable. n is the value of the TEX[0], C and B bits concatenated. The possible values of each NOSn bit are:

0

Memory region is Outer Shareable.

1

Memory region is Inner Shareable.

The value of this bit is ignored if the region is Normal or Device memory that is not Shareable.

[23:20] - Reserved, res0.
[19] NS1

Mapping of S = 1 attribute for Normal memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • Is mapped as Normal memory.

  • Has the S bit set to 1.

The possible values of the bit are:

0

Region is not Shareable.

1

Region is Shareable.

[18] NS0

Mapping of S = 0 attribute for Normal memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • Is mapped as Normal memory.

  • Has the S bit set to 0.

The possible values of the bit are the same as those given for the NS1 bit, bit[19].

[17] DS1

Mapping of S = 1 attribute for Device memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • Is mapped as Device memory.

  • Has the S bit set to 1.

Note

This field has no significance in the processor.

[16] DS0

Mapping of S = 0 attribute for Device memory. This bit gives the mapped Shareable attribute for a region of memory that:

  • Is mapped as Device memory.

  • Has the S bit set to 0.

Note

This field has no significance in the processor.

[2n+1:2n][a] TRn

Primary TEX mapping for memory attributes n. n is the value of the TEX[0], C and B bits, see Table 4.242. This field defines the mapped memory type for a region with attributes n. The possible values of the field are:

0b00

Device (nGnRnE).

0b01

Device (not nGnRnE).

0b10

Normal Memory.

0b11

Reserved, effect is unpredictable.

[a] Where n is 0-7.


Table 4.242 shows the mapping between the memory region attributes and the n value used in the PRRR.nOSn and PRRR.TRn field descriptions.

Table 4.242. Memory attributes and the n value for the PRRR field descriptions
Attributes n value
TEX[0] C B
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7

Large physical address translations use Long-descriptor translation table formats and MAIR0 replaces the PRRR, and MAIR1 replaces the NMRR. For more information see Memory Attribute Indirection Registers 0 and 1.

To access the PRRR:

	
MRC p15, 0, <Rt>, c10, c2, 0    ; Read PRRR into Rt
MCR p15, 0, <Rt>, c10, c2, 0    ; Write Rt to PRRR
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