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Reset Management Register

The RMR characteristics are:


Controls the execution state that the processor boots into and allows request of a warm reset.

Usage constraints

This register is accessible as follows:











(SCR.NS = 1)


(SCR.NS = 0)

- - - - - RW RW

This register is subject to CP15SDISABLE, that prevents writing to this register when the CP15SDISABLE signal is asserted.


The RMR is architecturally mapped to the AArch64 RMR_EL3 register.

There is one copy of this register that is used in both Secure and Non-secure states.


RMR is a 32-bit register.

Figure 4.136 shows the RMR bit assignments.

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Table 4.248 shows the RMR bit assignments.

Table 4.248. RMR bit assignments
Bits Name Function
[31:2] -

Reserved, res0.

[1] RR

Reset Request. The possible values are:


This is the reset value.


Requests a warm reset. This bit is set to 0 by either a cold or warm reset.

The bit is strictly a request.

The RR bit drives the WARMRSTREQ output signal.

[0] AA64[a]

Determines which execution state the processor boots into after a warm reset. The possible values are:


AArch32 Execution state.


AArch64 Execution state.

The reset vector address on reset takes a choice between two values, depending on the value in the AA64 bit. This ensures that even with reprogramming of the AA64 bit, it is not possible to change the reset vector to go to a different location.

[a] The cold reset value depends on the AA64nAA32 signal.

To access the RMR:

MRC p15,0,<Rt>,c12,c0,2 ; Read RMR into Rt
MCR p15,0,<Rt>,c12,c0,2 ; Write Rt to RMR

Register access is encoded as follows:

Table 4.249. RMR access encoding
coproc opc1 CRn CRm opc2
1111 000 1100 0000 010

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