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Revision ID Register

The REVIDR characteristics are:

Purpose

Provides implementation-specific minor revision information that can be interpreted only in conjunction with the Main ID Register.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO
Configurations

REVIDR is architecturally mapped to AArch64 register REVIDR_EL1. See Revision ID Register.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

REVIDR is a 32-bit register.

Figure 4.78 shows the REVIDR bit assignments.

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Table 4.162 shows the REVIDR bit assignments.

Table 4.162. REVIDR bit assignments
Bits Name Function
[31:0] ID number

Implementation-specific revision information. The reset value is determined by the specific Cortex-A53 MPCore implementation.

0x00000000

Revision code is zero.


To access the REVIDR:

	
MRC p15, 0, <Rt>, c0, c0, 6; Read REVIDR into Rt

Register access is encoded as follows:

Table 4.163. REVIDR access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0000 110

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