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Secure Configuration Register

The SCR characteristics are:

Purpose

Defines the configuration of the current security state. It specifies:

  • The security state of the processor, Secure or Non-secure.

  • What state the processor branches to, if an IRQ, FIQ or external abort occurs.

  • Whether the CPSR.F and CPSR.A bits can be modified when SCR.NS = 1.

Usage constraints

This register is accessible as follows:

EL0

NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW - RW RW

Any read or write to SCR in Secure EL1 state in AArch32 is trapped as an exception to EL3.

Configurations

The SCR is a Restricted access register that exists only in the Secure state.

The SCR is mapped to the AArch64 SCR_EL3 register.

Attributes

SCR is a 32-bit register.

Figure 4.101 shows the SCR bit assignments.

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Table 4.206 shows the SCR bit assignments.

Table 4.206. SCR bit assignments
Bits Name Function
[31:14] -

Reserved, res0.

[13] TWE

Trap WFE instructions. The possible values are:

0

WFE instructions are not trapped. This is the reset value.

1

WFE instructions executed in any mode other than Monitor mode are trapped to Monitor mode as undefined if the instruction would otherwise cause suspension of execution, that is if:

  • The event register is not set.

  • There is not a pending WFE wakeup event.

  • The instruction does not cause another exception.

[12] TWI

Trap WFI instructions. The possible values are:

0

WFI instructions are not trapped. This is the reset value.

1

WFI instructions executed in any mode other than Monitor mode are trapped to Monitor mode as undefined if the instruction would otherwise cause suspension of execution.

[11:10] -

Reserved, res0.

[9] SIF

Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetches from Non-secure memory. The possible values are:

0

Secure state instruction fetches from Non-secure memory permitted. This is the reset value.

1

Secure state instruction fetches from Non-secure memory not permitted.

[8] HCE

Hyp Call enable. This bit enables use of the HVC instruction from Non-secure EL1 modes. The possible values are:

0

The HVC instruction is undefined in any mode. This is the reset value.

1

The HVC instruction enabled in Non-secure EL1, and performs a Hyp Call.

[7] SCD

Secure Monitor Call disable. Makes the SMC instruction undefined in Non-secure state. The possible values are:

0

SMC executes normally in Non-secure state, performing a Secure Monitor Call. This is the reset value.

1

The SMC instruction is undefined in Non-secure state.

A trap of the SMC instruction to Hyp mode takes priority over the value of this bit.

[6] nET

Not Early Termination. This bit disables early termination.

This bit is not implemented, res0.

[5] AW

A bit writable. This bit controls whether CPSR.A can be modified in Non-secure state.

  • CPSR.A can be modified only in Secure state. This is the reset value.

  • CPSR.A can be modified in any security state.

[4] FW

F bit writable. This bit controls whether CPSR.F can be modified in Non-secure state:

  • CPSR.F can be modified only in Secure state. This is the reset value.

  • CPSR.F can be modified in any security state.

[3] EA

External Abort handler. This bit controls which mode takes external aborts. The possible values are:

0

External aborts taken in abort mode. This is the reset value.

1

External aborts taken in Monitor mode.

[2] FIQ

FIQ handler. This bit controls which mode takes FIQ exceptions. The possible values are:

0

FIQs taken in FIQ mode. This is the reset value.

1

FIQs taken in Monitor mode.

[1] IRQ

IRQ handler. This bit controls which mode takes IRQ exceptions. The possible values are:

0

IRQs taken in IRQ mode. This is the reset value.

1

IRQs taken in Monitor mode.

[0] NS

Non-secure bit. Except when the processor is in Monitor mode, this bit determines the security state of the processor. The possible values are:

0

Processor is in secure state. This is the reset value.

1

Processor is in non-secure state.


To access the SCR:

	
MRC p15,0,<Rt>,c1,c1,0 ; Read SCR into Rt
MCR p15,0,<Rt>,c1,c1,0 ; Write Rt to SCR
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