The SDCR characteristics are:
Controls debug and performance monitors functionality in Secure state.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - RW - RW RW
SDCR is mapped to AArch64 register MDCR_EL3.
SDCR is a 32-bit register.
Figure 4.104 shows the SDCR bit assignments.
Table 4.209 shows the SDCR bit assignments
External debugger access to Performance Monitors registers disabled. This disables access to these registers by an external debugger:
External debugger access to breakpoint and watchpoint registers disabled. This disables access to these registers by an external debugger:
Secure performance monitors enable. This allows event counting in Secure state:
AArch32 secure privileged debug. Enables or disables debug exceptions in Secure state, other than Software breakpoint instructions. The possible values are:
If debug exceptions from Secure EL1 are enabled, then debug exceptions from Secure EL0 are also enabled.
Otherwise, debug exceptions from Secure EL0 are enabled only if SDER32_EL3.SUIDEN is 1.
SPD is ignored in Non-secure state. Debug exceptions from Software breakpoint instruction debug events are always enabled.
To access the SDCR:
MRC p15,0,<Rt>,c1,c3,1 ; Read SDCR into Rt MCR p15,0,<Rt>,c1,c3,1 ; Write Rt to SDCR