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Translation Table Base Register 1

The TTBR1 characteristics are:

Purpose

Holds the base address of translation table 1, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses from modes other than Hyp mode.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

Used in conjunction with the TTBCR. When the 64-bit TTBR1 format is used, cacheability and shareability information is held in the TTBCR and not in TTBR1. See Translation Table Base Control Register.

Configurations

TTBR1 (NS) is architecturally mapped to AArch64 register TTBR0_EL1. See Translation Table Base Register 1.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

Attributes

TTBR1 is:

  • A 32-bit register when TTBCR.EAE is 0.

  • A 64-bit register when TTBCR.EAE is 1.

There are two formats for this register. TTBCR.EAE determines which format of the register is used. This section describes:

TTBR1 format when using the Short-descriptor translation table format

Figure 4.113 shows the TTBR1 bit assignments when TTBCR.EAE is 0.

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Table 4.218 shows the TTBR1 bit assignments when TTBCR.EAE is 0.

Table 4.218. TTBR1 bit assignments, TTBCR.EAE is 0
Bits Name Function
[31:7] TTB1

Translation table base 1 address, bits[31:x], where x is 14-(TTBCR.N). Bits [x-1:7] are res0.

The translation table must be aligned on a 16KByte boundary.

If bits [x-1:7] are not all zero, this is a misaligned Translation Table Base Address. Its effects are constrained unpredictable, where bits [x-1:7] are treated as if all the bits are zero. The value read back from those bits is the value written.

[6] - Reserved, res0.
[5] NOS

Not Outer Shareable bit. Indicates the Outer Shareable attribute for the memory associated with a translation table walk that has the Shareable attribute, indicated by TTBR0.S is 1. The possible values are:

0

Outer Shareable.

1

Inner Shareable.

This bit is ignored when TTBR0.S is 0.

[4:3] RGN

Region bits. Indicates the Outer cacheability attributes for the memory associated with the translation table walks. The possible values are:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[2] IMP Reserved, res0.
[1] S

Shareable bit. Indicates the Shareable attribute for the memory associated with the translation table walks. The possible values are:

0

Non-shareable.

1

Shareable.

[0] C

Cacheable bit. Indicates whether the translation table walk is to Inner Cacheable memory.

0

Inner Non-cacheable

1

Inner Cacheable.


To access the TTBR1 when TTBCR.EAE is 0:

	
MRC p15, 0, <Rt>, c2, c0, 1 ; Read TTBR1 into Rt
MCR p15, 0, <Rt>, c2, c0, 1 ; Write Rt to TTBR1

TTBR1 format when using the Long-descriptor translation table format

Figure 4.114 shows the TTBR1 bit assignments when TTBCR.EAE is 1.

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Table 4.219 shows the TTBR1 bit assignments when TTBCR.EAE is 1.

Table 4.219. TTBR1 bit assignments, TTBCR.EAE is 1
Bits Name Function
[63:56] -

Reserved, res0.

[55:48] ASID

An ASID for the translation table base address. The TTBCR.A1 field selects either TTBR0.ASID or TTBR1.ASID.

[47:0] BADDR[47:x]

Translation table base address, bits[47:x]. Bits [x-1:0] are res0.

x is based on the value of TTBCR.T0SZ, and is calculated as follows:

  • If TTBCR.T0SZ is 0 or 1, x = 5 - TTBCR.T0SZ.

  • If TTBCR.T0SZ is greater than 1, x = 14 - TTBCR.T0SZ.

The value of x determines the required alignment of the translation table, that must be aligned to 2x bytes.

If bits [x-1:3] are not all zero, this is a misaligned Translation Table Base Address. Its effects are constrained unpredictable, where bits [x-1:0] are treated as if all the bits are zero. The value read back from those bits is the value written.


To access the 64-bit TTBR1 when TTBCR.EAE = 1:

	
MRRC p15, 1, <Rt>, <Rt2>, c2 ; Read 64-bit TTBR1 into Rt (low word) and Rt2 (high word)
MCRR p15, 1, <Rt>, <Rt2>, c2 ; Write Rt (low word) and Rt2 (high word) to 64-bit TTBR1
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