You copied the Doc URL to your clipboard.

Vector Base Address Register

The VBAR characteristics are:

Purpose

Holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode when high exception vectors are not selected.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RW RW RW RW RW

Software must program the Non-secure instance of the register with the required initial value as part of the processor boot sequence.

Configurations

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

The Non-secure VBAR is architecturally mapped to the AArch64 VBAR_EL1 register. See Vector Base Address Register, EL2.

The Secure VBAR is mapped to AArch64 register VBAR_EL3[31:0]. See Vector Base Address Register, EL3.

VBAR has write access to the Secure instance of the register disabled when the CP15SDISABLE signal is asserted HIGH.

Attributes

VBAR is a 32-bit register.

See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

To access the VBAR:

	
MRC p15, 0, <Rt>, c12, c0, 0 ; Read VBAR into Rt
MCR p15, 0, <Rt>, c12, c0, 0 ; Write Rt to VBAR
Was this page helpful? Yes No