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AArch32 register summary

In AArch32 state you access the system registers through a conceptual coprocessor, identified as CP15, the System Control Coprocessor. Within CP15, there is a top-level grouping of system registers by a primary coprocessor register number, c0-c15. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information about using the conceptual System Control Coprocessor in a VMSA context.

The system register space includes System operations system registers and System operations. The description of the system register space describes the permitted access, RO, WO, or RW, to each register or operation.

The following sections describe the CP15 system control registers grouped by CRn order, and are accessed by the MCR and MRC instructions.

The following subsection describes the 64-bit registers and provides cross-references to individual register descriptions:

In addition to listing the CP15 system registers by CRn ordering, the following subsections describe the CP15 system registers by functional group:

Table 4.129 describes the column headings in the CP15 register summary tables use throughout this section.

Table 4.129. System register field values
Heading Description
CRn System control primary register number.
Op1 Arguments to the register access instruction.
Name The name of the register or operation. Some assemblers support aliases that you can use to access the registers and operations by name.
Reset Reset value of register.
Description Cross-reference to the register description.

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