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AArch32 Address registers

Table 4.151 shows the address translation register and operations. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.151. Address translation operations
Name CRn Op1 CRm Op2 Reset Width Description
PAR c7 0 c4 0



Physical Address Register

-   c7 - 64-bit

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