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AArch32 Fault handling registers

Table 4.149 shows the Fault handling registers in the AArch32 Execution state.

Table 4.149. Fault handling registers
Name CRn Op1 CRm Op2 Reset Description
DFSR c5 0 c0 0 UNK

Data Fault Status Register

IFSR       1 UNK

Instruction Fault Status Register

ADFSR     c1 0 0x00000000

Auxiliary Data Fault Status Register

AIFSR       1 0x00000000

Auxiliary Instruction Fault Status Register

DFAR c6 0 c0 0 UNK

Data Fault Address Register, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile

IFAR       2 UNK

Instruction Fault Address Register, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile


The Virtualization registers include additional fault handling registers. For more information see AArch32 Virtualization registers.

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