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AArch32 Identification registers

Table 4.147 shows the identification registers.

Table 4.147. Identification registers
Name CRn Op1 CRm Op2 Reset Description
MIDR c0 0 c0 0 0x410FD034

Main ID Register
CTR       1 0x84448004

Cache Type Register
TCMTR       2 0x00000000

TCM Type Register
TLBTR       3 0x00000000

TLB Type Register
MPIDR       5 -[a]

Multiprocessor Affinity Register
REVIDR       6 0x00000000 Revision ID Register
ID_PFR0     c1 0 0x00000131

Processor Feature Register 0
ID_PFR1       1 0x10011011[b]

Processor Feature Register 0
ID_DFR0       2 0x03010066

Debug Feature Register 0
ID_AFR0       3 0x00000000 Auxiliary Feature Register 0
ID_MMFR0       4 0x10201105

Memory Model Feature Register 0
ID_MMFR1       5 0x40000000

Memory Model Feature Register 1
ID_MMFR2       6 0x01260000

Memory Model Feature Register 2
ID_MMFR3       7 0x02102211

Memory Model Feature Register 3
ID_ISAR0     c2 0 0x02101110

Instruction Set Attribute Register 0
ID_ISAR1       1 0x13112111

Instruction Set Attribute Register 1
ID_ISAR2       2 0x21232042

Instruction Set Attribute Register 2
ID_ISAR3       3 0x01112131

Instruction Set Attribute Register 3
ID_ISAR4       4 0x00011142

Instruction Set Attribute Register 4
ID_ISAR5 c0 0 c2 5 0x00011121[c]

Instruction Set Attribute Register 5
CCSIDR   1 c0 0 -

Cache Size ID Register
CLIDR       1 0x0A200023[d]

Cache Level ID Register
AIDR       7 0x00000000

Auxiliary ID Register
CSSELR   2 c0 0 0x00000000 Cache Size Selection Register

[a] The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the device implements.

[b] Bits [31:28] are 0x1 if the GIC CPU interface is enabled, and 0x0 otherwise.

[c] ID_ISAR5 has the value 0x00010001 if the Cryptography Extension is not implemented and enabled.

[d] The value is 0x09200003 if the L2 cache is not implemented.


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