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AArch32 Identification registers
Table 4.147 shows the identification registers.
Name | CRn | Op1 | CRm | Op2 | Reset | Description |
---|---|---|---|---|---|---|
MIDR | c0 | 0 | c0 | 0 | 0x410FD034 |
|
CTR | 1 | 0x84448004 |
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TCMTR | 2 | 0x00000000 |
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TLBTR | 3 | 0x00000000 |
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MPIDR | 5 | -[a] | ||||
REVIDR | 6 | 0x00000000 |
Revision ID Register | |||
ID_PFR0 | c1 | 0 | 0x00000131 |
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ID_PFR1 | 1 | 0x10011011 [b] |
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ID_DFR0 | 2 | 0x03010066 |
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ID_AFR0 | 3 | 0x00000000 |
Auxiliary Feature Register 0 | |||
ID_MMFR0 | 4 | 0x10201105 |
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ID_MMFR1 | 5 | 0x40000000 |
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ID_MMFR2 | 6 | 0x01260000 |
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ID_MMFR3 | 7 | 0x02102211 |
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ID_ISAR0 | c2 | 0 | 0x02101110 |
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ID_ISAR1 | 1 | 0x13112111 |
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ID_ISAR2 | 2 | 0x21232042 |
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ID_ISAR3 | 3 | 0x01112131 |
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ID_ISAR4 | 4 | 0x00011142 |
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ID_ISAR5 | c0 | 0 | c2 | 5 | 0x00011121 [c] |
|
CCSIDR | 1 | c0 | 0 | - | ||
CLIDR | 1 | 0x0A200023 [d] |
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AIDR | 7 | 0x00000000 |
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CSSELR | 2 | c0 | 0 | 0x00000000 |
Cache Size Selection Register | |
[a] The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the device implements. [b] Bits
[31:28] are [c] ID_ISAR5
has the value [d] The
value is |