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AArch32 Implementation defined registers

Table 4.157 shows the 32-bit wide implementation defined registers. These registers provide test features and any required configuration options specific to the Cortex-A53 processor.

Table 4.157. Memory access registers
Name CRn Op1 CRm Op2 Reset Description
L2CTLR c9 1 c0 2 -[a]

Control Register

L2ECTLR 3 0x00000000 Extended Control Register
L2ACTLR c15 1 c0 0 0x80000000[b] Auxiliary Control Register
CBAR c3 0 -[a] Configuration Base Address Register
CDBGDR0 3[c] c0 0 UNK Data Register 0, see Direct access to internal memory
CDBGDR1     1 UNK Data Register 1, see Direct access to internal memory
CDBGDR2     2 UNK Data Register 2, see Direct access to internal memory
CDBGDCT   c2 0 UNK Data Cache Tag Read Operation Register, see Direct access to internal memory
CDBGICT     1 UNK Instruction Cache Tag Read Operation Register, see Direct access to internal memory
CDBGDCD     c4 0 UNK Data Cache Data Read Operation Register, see Direct access to internal memory
CDBGICD   c4 1 UNK Instruction Cache Data Read Operation Register, see Direct access to internal memory
CDBGTD     2 UNK TLB Data Read Operation Register, see Direct access to internal memory
CPUACTLR - 0 c15 - 0x00000000090CA000 CPU Auxiliary Control Register
CPUECTLR - 1 c15 - 0x0000 0000 0000 0000 CPU Extended Control Register
CPUMERRSR - 2 c15 - - CPU Memory Error Syndrome Register
L2MERRSR - 3 c15 - - Memory Error Syndrome Register

[a] The reset value depends on the processor configuration.

[b] This is the reset value for an ACE interface. For a CHI interface the reset value is 0x 80004008.

[c] See Direct access to internal memory for information on how these registers are used.


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