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AArch32 Secure registers

Table 4.154 shows the Secure registers. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.154. Security registers
Name CRn Op1 CRm Op2 Reset Description
SCR c1 0 c1 0 0x00000000

Secure Configuration Register

SDER       1 UNK Secure Debug Enable Register
NSACR       2


Non-Secure Access Control Register

VBAR c12 0 c0 0


Vector Base Address Register

MVBAR       1 UNK

Monitor Vector Base Address Register

ISR     c1 0 UNK

Interrupt Status Register

[a] If EL3 is AArch64 then the NSACR reads as 0x00000C00.

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