You copied the Doc URL to your clipboard.

AArch32 Virtual memory control registers

Table 4.148 shows the virtual memory control registers.

Table 4.148. Virtual memory control registers
Name CRn Op1 CRm Op2 Reset Width Description
SCTLR c1 0 c0 0 0x00C50838[a] 32-bit

System Control Register

TTBR0 c2 0 c0 0 UNK 32-bit Translation Table Base Register 0, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
- 0 c2 - 64-bit
TTBR1   0 c0 1 UNK 32-bit Translation Table Base Register 1, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
- 1 c2 - 64-bit
TTBCR   0 c0 2

0x00000000[b]

32-bit

Translation Table Base Control Register

DACR c3 0 c0 0 UNK 32-bit Domain Access Control Register
PRRR c10 0 c2 0 UNK 32-bit Primary Region Remap Register
MAIR0   0 UNK 32-bit

Memory Attribute Indirection Registers 0 and 1

NMRR   1 UNK 32-bit

Normal Memory Remap Register

MAIR1   1 UNK 32-bit Memory Attribute Indirection Registers 0 and 1
AMAIR0 c3 0 0x00000000 32-bit Auxiliary Memory Attribute Indirection Register 0
AMAIR1 1 0x00000000 32-bit Auxiliary Memory Attribute Indirection Register 1
CONTEXTIDR c13 0 c0 1 UNK 32-bit

Process ID Register, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile

[a] The reset value depends on inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4.148 assumes these signals are set to LOW.

[b] The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is 0x0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.


Was this page helpful? Yes No