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c0 registers

Table 4.130 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c0.

Table 4.130. c0 register summary
CRn Op1 CRm Op2 Name Reset Description
c0 0 c0 0 MIDR 0x410FD034

Main ID Register
1 CTR 0x84448004

Cache Type Register
2 TCMTR 0x00000000

TCM Type Register
3 TLBTR 0x00000000

TLB Type Register
4, 7 MIDR 0x410FD034

Aliases of Main ID Register, Main ID Register
5 MPIDR -[a]

Multiprocessor Affinity Register
6 REVIDR 0x00000000 Revision ID Register
c1 0 ID_PFR0 0x00000131

Processor Feature Register 0
1 ID_PFR1 0x10011011[b]

Processor Feature Register 1
2 ID_DFR0 0x03010066

Debug Feature Register 0
3 ID_AFR0 0x00000000 Auxiliary Feature Register 0
4 ID_MMFR0 0x10201105

Memory Model Feature Register 0
5 ID_MMFR1 0x40000000

Memory Model Feature Register 1
6 ID_MMFR2 0x01260000

Memory Model Feature Register 2
7 ID_MMFR3 0x02102211

Memory Model Feature Register 3
c2 0 ID_ISAR0 0x02101110

Instruction Set Attribute Register 0
1 ID_ISAR1 0x13112111

Instruction Set Attribute Register 1
2 ID_ISAR2 0x21232042

Instruction Set Attribute Register 2
3 ID_ISAR3 0x01112131

Instruction Set Attribute Register 3
0 c2 4 ID_ISAR4 0x00011142

Instruction Set Attribute Register 4
5 ID_ISAR5 0x00011121[c]

Instruction Set Attribute Register 5
1 c0 0 CCSIDR -

Cache Size ID Register
1 CLIDR 0x0A200023[d]

Cache Level ID Register
7 AIDR 0x00000000

Auxiliary ID Register
2 c0 0 CSSELR 0x00000000 Cache Size Selection Register
4 c0 0 VPIDR 0x410FD034

Virtualization Processor ID Register
5 VMPIDR -[e] Virtualization Multiprocessor ID Register

[a] The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the device implements.

[b] Bits [31:28] are 0x1 if the GIC CPU interface is enabled, and 0x0 otherwise.

[c] ID_ISAR5 has the value 0x00010001 if the Cryptography Extension is not implemented and enabled.

[d] The value is 0x09200003 if the L2 cache is not implemented.

[e] The reset value is the value of the Multiprocessor Affinity Register.


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