c0 registers
Table 4.130 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c0.
CRn | Op1 | CRm | Op2 | Name | Reset | Description |
---|---|---|---|---|---|---|
c0 | 0 | c0 | 0 | MIDR | 0x410FD034 |
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1 | CTR | 0x84448004 |
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2 | TCMTR | 0x00000000 |
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3 | TLBTR | 0x00000000 |
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4, 7 | MIDR | 0x410FD034 |
Aliases of Main ID Register, Main ID Register |
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5 | MPIDR | -[a] | ||||
6 | REVIDR | 0x00000000 |
Revision ID Register | |||
c1 | 0 | ID_PFR0 | 0x00000131 |
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1 | ID_PFR1 | 0x10011011 [b] |
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2 | ID_DFR0 | 0x03010066 |
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3 | ID_AFR0 | 0x00000000 |
Auxiliary Feature Register 0 | |||
4 | ID_MMFR0 | 0x10201105 |
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5 | ID_MMFR1 | 0x40000000 |
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6 | ID_MMFR2 | 0x01260000 |
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7 | ID_MMFR3 | 0x02102211 |
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c2 | 0 | ID_ISAR0 | 0x02101110 |
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1 | ID_ISAR1 | 0x13112111 |
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2 | ID_ISAR2 | 0x21232042 |
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3 | ID_ISAR3 | 0x01112131 |
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0 | c2 | 4 | ID_ISAR4 | 0x00011142 |
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5 | ID_ISAR5 | 0x00011121 [c] |
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1 | c0 | 0 | CCSIDR | - | ||
1 | CLIDR | 0x0A200023 [d] |
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7 | AIDR | 0x00000000 |
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2 | c0 | 0 | CSSELR | 0x00000000 |
Cache Size Selection Register | |
4 | c0 | 0 | VPIDR | 0x410FD034 |
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5 | VMPIDR | -[e] | Virtualization Multiprocessor ID Register | |||
[a] The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the device implements. [b] Bits
[31:28] are [c] ID_ISAR5
has the value [d] The
value is [e] The reset value is the value of the Multiprocessor Affinity Register. |