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c1 registers

Table 4.131 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c1.

Table 4.131. c1 register summary
CRn Op1 CRm Op2 Name Reset Description
c1 0 c0 0 SCTLR 0x00C50838[a]

System Control Register

1 ACTLR

0x00000000

Auxiliary Control Register

2 CPACR 0x00000000

Architectural Feature Access Control Register

c1 0 SCR 0x00000000

Secure Configuration Register

1 SDER 0x00000000

Secure Debug Enable Register

2 NSACR

0x00000000[b]

Non-Secure Access Control Register

c3 1 SDCR 0x00000000 Secure Debug Control Register
4 c0 0 HSCTLR 0x03C50838

Hyp System Control Register

1 HACTLR 0x00000000 Auxiliary Control Register, EL2
c1 0 HCR 0x00000000

Hyp Configuration Register

1 HDCR 0x00000006

Hyp Debug Control Register

2 HCPTR 0x000033FF[c]

Hyp Architectural Feature Trap Register

3 HSTR 0x00000000

Hyp System Trap Register

4 HCR2 0x00000000 Hyp Configuration Register 2
7 HACR 0x00000000 Hyp Architectural Feature Trap Register

[a] The reset value depends on inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4.130 assumes these signals are set to LOW.

[b] If EL3 is AArch64 then the NSACR reads as 0x00000C00.

[c] The reset value depends on the FPU and NEON configuration. If Advanced SIMD and Floating-point are implemented, the reset value is 0x000033FF. If Advanced SIMD and Floating-point are not implemented, the reset value is 0x0000BFFF.


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