You copied the Doc URL to your clipboard.

c14 registers

Table 4.144 shows the CP15 system registers when the processor is in AArch32 state and the value of CRn is c14. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.144. c14 register summary
Op1 CRm Op2 Name Reset Description
0 c0 0 CNTFRQ UNK

Timer Counter Frequency Register

  c1 0 CNTKCTL -[a]

Timer Control Register

  c2 0 CNTP_TVAL UNK

Physical Timer TimerValue Register

    1 CNTP_CTL

-[b]

Physical Timer Control Register

  c3 0 CNTV_TVAL UNK

Virtual Timer TimerValue Register

    1 CNTV_CTL -[b]

Counter-timer Virtual Timer Control Register

  c8 0 PMEVCNTR0 UNK Performance Monitor Event Count Registers
    1 PMEVCNTR1 UNK
    2 PMEVCNTR2 UNK
    3 PMEVCNTR3 UNK
    4 PMEVCNTR4 UNK
    5 PMEVCNTR5 UNK
  c12 0 PMEVTYPER0 UNK

Performance Monitor Event Type Registers

    1 PMEVTYPER1 UNK
    2 PMEVTYPER2 UNK
    3 PMEVTYPER3 UNK
    4 PMEVTYPER4 UNK
    5 PMEVTYPER5 UNK
  c15 7 PMCCFILTR 0x00000000 Performance Monitor Cycle Count Filter Register.
4 c1 0 CNTHCTL

-[c]

Timer Control Register (EL2)
  c2 0 CNTHP_TVAL UNK Physical Timer TimerValue (EL2)
    1 CNTHP_CTL -[b] Physical Timer Control Register (EL2)

[a] The reset value for bits[9:8, 2:0] is 0b00000.

[b] The reset value for bit[0] is 0.

[c] The reset value for bit[2] is 0 and for bits[1:0] is 0b11.


Was this page helpful? Yes No