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c15 registers

Table 4.145 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c15.

Table 4.145. c15 register summary
Op1 CRm Op2 Name Reset Description
1 c0 0 L2ACTLR 0x80000000[a] Auxiliary Control Register
c3 0 CBAR -[b] Configuration Base Address Register
3 c0 0 CDBGDR0 UNK Cache Debug Data Register 0, see Direct access to internal memory
1 CDBGDR1 UNK Cache Debug Data Register 1, see Direct access to internal memory
2 CDBGDR2 UNK Cache Debug Data Register 2, see Direct access to internal memory
3 CDBGDR3 UNK Cache Debug Data Register 3, see Direct access to internal memory
c2 0 CDBGDCT UNK Cache Debug Data Cache Tag Read Operation Register, see Direct access to internal memory
1 CDBGICT UNK Cache Debug Instruction Cache Tag Read Operation Register, see Direct access to internal memory
c4 0 CDBGDCD UNK Cache Debug Cache Debug Data Cache Data Read Operation Register, see Direct access to internal memory
1 CDBGICD UNK Cache Debug Instruction Cache Data Read Operation Register, see Direct access to internal memory
2 CDBGTD UNK Cache Debug TLB Data Read Operation Register, see Direct access to internal memory

[a] This is the reset value for an ACE interface. For a CHI interface the reset value is 0x 80004008.

[b] The reset value depends on the processor configuration.


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