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c9 registers

Table 4.140 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c9. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.140. c9 register summary
CRn Op1 CRm Op2 Name Reset Description
c9 0 c12 0 PMCR 0x41033000

Performance Monitors Control Register

1 PMNCNTENSET UNK

Performance Monitors Count Enable Set Register

2 PMNCNTENCLR UNK

Performance Monitors Count Enable Clear Register

3 PMOVSR UNK

Performance Monitor Overflow Flag Status Clear Register

4 PMSWINC UNK

Performance Monitors Software Increment Register

5 PMSELR UNK

Performance Monitors Event Counter Selection Register

6 PMCEID0 0x67FFBFFF[a] Performance Monitors Common Event Identification Register 0
7 PMCEID1 0x00000000 Performance Monitors Common Event Identification Register 1
c13 0 PMCCNTR UNK

Performance Monitors Cycle Counter

1

PMXEVTYPER

UNK Performance Monitors Selected Event Type and Filter Register
2 PMXEVCNTR UNK Performance Monitors Selected Event Counter Register
c14 0 PMUSERENR 0x00000000

Performance Monitors User Enable Register

1 PMINTENSET UNK Performance Monitors Interrupt Enable Set Register
2 PMINTENCLR UNK

Performance Monitors Interrupt Enable Clear Register

3 PMOVSSET UNK

Performance Monitor Overflow Flag Status Set Register

1 c0 2 L2CTLR -[b]

Control Register

3 L2ECTLR 0x00000000 Extended Control Register

[a] The reset value is 0x663FBFFF if L2 cache is not implemented.

[b] The reset value depends on the processor configuration.


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