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AArch32 Instruction Set Attribute Register 0

The ID_ISAR0_EL1 characteristics are:

Purpose

Provides information about the instruction sets implemented by the processor in AArch32.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RO RO RO RO RO
Configurations

ID_ISAR0_EL1 is architecturally mapped to AArch32 register ID_ISAR0. See Instruction Set Attribute Register 0.

Attributes

ID_ISAR0_EL1 is a 32-bit register.

Figure 4.11 shows the ID_ISAR0_EL1 bit assignments.

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Table 4.38 shows the ID_ISAR0_EL1 bit assignments.

Table 4.38. ID_ISAR0_EL1 bit assignments
Bits Name Function
[31:28] -

Reserved, res0.

[27:24] Divide

Indicates the implemented Divide instructions:

0x2
  • SDIV and UDIV in the T32 instruction set.

  • SDIV and UDIV in the A32 instruction set.

[23:20] Debug

Indicates the implemented Debug instructions:

0x1

BKPT.

[19:16] Coproc

Indicates the implemented Coprocessor instructions:

0x0

None implemented, except for separately attributed by the architecture including CP15, CP14, Advanced SIMD and Floating-point.

[15:12] CmpBranch

Indicates the implemented combined Compare and Branch instructions in the T32 instruction set:

0x1

CBNZ and CBZ.

[11:8] Bitfield

Indicates the implemented bit field instructions:

0x1

BFC, BFI, SBFX, and UBFX.

[7:4] BitCount

Indicates the implemented Bit Counting instructions:

0x1

CLZ.

[3:0] Swap

Indicates the implemented Swap instructions in the A32 instruction set:

0x0

None implemented.


To access the ID_ISAR0_EL1:

	
MRS <Xt>, ID_ISAR0_EL1 ; Read ID_ISAR0_EL1 into Xt

Register access is encoded as follows:

Table 4.39. ID_ISAR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 000

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