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AArch32 Memory Model Feature Register 1

The ID_MMFR1_EL1 characteristics are:

Purpose

Provides information about the memory model and memory management support in AArch32.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RO RO RO RO RO
Configurations

ID_MMFR1_EL1 is architecturally mapped to AArch32 register ID_MMFR1. See Memory Model Feature Register 1.

Attributes

ID_MMFR1_EL1 is a 32-bit register.

Figure 4.8 shows the ID_MMFR1_EL1 bit assignments.

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Table 4.32 shows the ID_MMFR1_EL1 bit assignments.

Table 4.32. ID_MMFR1_EL1 bit assignments
Bits Name Function
[31:28] BPred

Indicates branch predictor management requirements:

0x4

For execution correctness, branch predictor requires no flushing at any time.

[27:24] L1TstCln

Indicates the supported L1 Data cache test and clean operations, for Harvard or unified cache implementation:

0x0

None supported.

[23:20] L1Uni

Indicates the supported entire L1 cache maintenance operations, for a unified cache implementation:

0x0

None supported.

[19:16] L1Hvd

Indicates the supported entire L1 cache maintenance operations, for a Harvard cache implementation:

0x0

None supported.

[15:12] L1UniSW

Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache implementation:

0x0

None supported.

[11:8] L1HvdSW

Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache implementation:

0x0

None supported.

[7:4] L1UniVA

Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache implementation:

0x0

None supported.

[3:0] L1HvdVA

Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache implementation:

0x0

None supported.


To access the ID_MMFR1_EL1:

	
MRS <Xt>, ID_MMFR1_EL1 ; Read ID_MMFR1_EL1 into Xt

Register access is encoded as follows:

Table 4.33. ID_MMFR1_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0001 101

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