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AArch32 Memory Model Feature Register 2

The ID_MMFR2_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch32.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RO RO RO RO RO
Configurations

ID_MMFR2_EL1 is architecturally mapped to AArch32 register ID_MMFR2. See Memory Model Feature Register 2.

Attributes

ID_MMFR2_EL1 is a 32-bit register.

Figure 4.9 shows the ID_MMFR2_EL1 bit assignments.

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Table 4.34 shows the ID_MMFR2_EL1 bit assignments.

Table 4.34. ID_MMFR2_EL1 bit assignments
Bits Name Function
[31:28] HWAccFlg

Hardware access flag. Indicates support for a hardware access flag, as part of the VMSAv7 implementation:

0x0

Not supported.

[27:24] WFIStall

Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:

0x1

Support for WFI stalling.

[23:20] MemBarr

Memory Barrier. Indicates the supported CP15 memory barrier operations.

0x2

Supported CP15 memory barrier operations are:

  • Data Synchronization Barrier (DSB).

  • Instruction Synchronization Barrier (ISB).

  • Data Memory Barrier (DMB).

[19:16] UniTLB

Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation.

0x6

Supported unified TLB maintenance operations are:

  • Invalidate all entries in the TLB.

  • Invalidate TLB entry by MVA.

  • Invalidate TLB entries by ASID match.

  • Invalidate instruction TLB and data TLB entries by MVA All ASID. This is a shared unified TLB operation.

  • Invalidate Hyp mode unified TLB entry by MVA.

  • Invalidate entire Non-secure EL1 and EL0 unified TLB.

  • Invalidate entire Hyp mode unified TLB.

  • TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, and TLBIMVALH.

  • TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, and TLBIIPAS2L.

[15:12] HvdTLB

Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB implementation:

0x0

Not supported.

[11:8] LL1HvdRng

L1 Harvard cache Range. Indicates the supported L1 cache maintenance range operations, for a Harvard cache implementation:

0x0

Not supported.

[7:4] L1HvdBG

L1 Harvard cache Background fetch. Indicates the supported L1 cache background prefetch operations, for a Harvard cache implementation:

0x0

Not supported.

[3:0] L1HvdFG

L1 Harvard cache Foreground fetch. Indicates the supported L1 cache foreground prefetch operations, for a Harvard cache implementation:

0x0

Not supported.


To access the ID_MMFR2_EL1:

	
MRS <Xt>, ID_MMFR2_EL1 ; Read ID_MMFR2_EL1 into Xt

Register access is encoded as follows:

Table 4.35. ID_MMFR2_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0001 110

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