The ID_PFR0_EL1 characteristics are:
Gives top-level information about the instruction sets supported by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_PFR0_EL1 is architecturally mapped to AArch32 register ID_PFR0. See Processor Feature Register 0.
ID_PFR0_EL1 is a 32-bit register.
Figure 4.4 shows the ID_PFR0_EL1 bit assignments.
Table 4.24 shows the ID_PFR0_EL1 bit assignments.
Indicates support for Thumb Execution Environment (T32EE) instruction set. This value is:
Indicates support for Jazelle. This value is:
Indicates support for T32 instruction set. This value is:
Indicates support for A32 instruction set. This value is:
To access the ID_PFR0_EL1:
MRS <Xt>, ID_PFR0_EL1 ; Read ID_PFR0_EL1 into Xt
Register access is encoded as follows: