You copied the Doc URL to your clipboard.

AArch64 Debug Feature Register 0, EL1

The ID_AA64DFR0_EL1 characteristics are:

Purpose

Provides top level information of the debug system in the AArch64 Execution state.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RO RO RO RO RO
Configurations

ID_AA64DFR0_EL1 is architecturally mapped to external register ID_AA64DFR0.

Attributes

ID_AA64DFR0_EL1 is a 64-bit register.

Figure 4.18 shows the ID_AA64DFR0_EL1 bit assignments.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.52 shows the ID_AA64DFR0_EL1 bit assignments.

Table 4.52. ID_AA64DFR0_EL1 bit assignments
Bits Name Function
[63:32] -

Reserved, res0.

[31:28] CTX_CMPs

Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints:

0b0001

Two breakpoints are context-aware.

[27:24] - Reserved, res0.
[23:20] WRPs

The number of watchpoints minus 1:

0b0011

Four watchpoints.

[19:16] - Reserved, res0.
[15:12] BRPs

The number of breakpoints minus 1:

0b0101

Six breakpoints.

[11:8] PMUver

Performance Monitors extension version.

0b0001

Performance monitor system registers implemented, PMUv3.

[7:4] Tracever

Trace extension:

0b0000

Trace system registers not implemented.

[3:0] Debugger

Debug architecture version:

0b0110

ARMv8-A debug architecture implemented.


To access the ID_AA64DFR0_EL1:

	
MRS <Xt>, ID_AA64DFR0_EL1 ; Read ID_AA64DFR0_EL1 into Xt

Register access is encoded as follows:

Table 4.53. ID_AA64DFR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0101 000

Was this page helpful? Yes No