You copied the Doc URL to your clipboard.

AArch64 Memory Model Feature Register 0, EL1

The ID_AA64MMFR0_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in the AArch64 Execution state.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RO RO RO RO RO
Configurations

ID_AA64MMFR0_EL1 is architecturally mapped to external register ID_AA64MMFR0_EL1.

Attributes

ID_AA64MMFR0_EL1 is a 64-bit register.

Figure 4.20 shows the ID_AA64MMFR0_EL1 bit assignments.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.56 shows the ID_AA64MMFR0_EL1 bit assignments.

Table 4.56. ID_AA64MMFR0_EL1 bit assignments
Bits Name Function
[63:32] -

Reserved, res0.

[31:28] TGran4

Support for 4 KB memory translation granule size:

0x0

Indicates that the 4KB granule is supported.

[27:24] TGran64

Support for 64 KB memory translation granule size:

0x0

Indicates that the 64KB granule is supported.

[23:20] TGran16

Support for 16 KB memory translation granule size:

0x0

Indicates that the 16KB granule is not supported.

[19:16] BigEndEL0

Mixed-endian support only at EL0.

res0

[15:12] SNSMem

Secure versus Non-secure Memory distinction:

0b0001

Supports a distinction between Secure and Non-secure Memory.

[11:8] BigEnd

Mixed-endian configuration support:

0b0001

Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits are RW.

[7:4] ASIDBits

Number of ASID bits:

0b0010

16 bits.

[3:0] PARange

Physical address range supported:

0b0010

40 bits, 1 TB.


To access the ID_AA64MMFR0_EL1:

	
MRS <Xt>, ID_AA64MMFR0_EL1 ; Read ID_AA64MMFR0_EL1 into Xt

Register access is encoded as follows:

Table 4.57. ID_AA64MMFR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0111 000

Was this page helpful? Yes No