You copied the Doc URL to your clipboard.

AArch64 Processor Feature Register 0

The ID_AA64PFR0_EL1 characteristics are:

Purpose

Provides additional information about implemented processor features in AArch64.

Note

The optional Advanced SIMD and Floating-point extension is not included in the base product of the processor. ARM requires licensees to have contractual rights to obtain the Advanced SIMD and Floating-point extension.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RO RO RO RO RO
Configurations

ID_AA64PFR0_EL1 is architecturally mapped to external register ID_AA64PFR0_EL1.

Attributes

ID_AA64PFR0_EL1 is a 64-bit register.

Figure 4.17 shows the ID_AA64PFR0_EL1 bit assignments.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.50 shows the ID_AA64PFR0_EL1 bit assignments.

Table 4.50. ID_AA64PFR0_EL1 bit assignments
Bits Name Function
[63:28] -

Reserved, res0.

[27:24] GIC

GIC CPU interface:

0x0

GIC CPU interface is disabled.

0x1

GIC CPU interface is implemented.

[23:20] FP[a]

Floating-point. The possible values are:

0x0

Floating-point is implemented.

0xF

Floating-point is not implemented.

[19:16] AdvSIMD[a]

Advanced SIMD. The possible values are:

0x0

Advanced SIMD is implemented.

0xF

Advanced SIMD is not implemented.

[15:12] EL3 handling

EL3 exception handling:

0x2

Instructions can be executed at EL3 in AArch64 or AArch32 state.

[11:8] EL2 handling

EL2 exception handling:

0x2

Instructions can be executed at EL2 in AArch64 or AArch32 state.

[7:4] EL1 handling

EL1 exception handling. The possible values are:

0x2

Instructions can be executed at EL1 in AArch64 or AArch32 state.

[3:0] EL0 handling

EL0 exception handling. The possible values are:

0x2

Instructions can be executed at EL0 in AArch64 or AArch32 state.

[a] The FP and AdvSIMD both take the same value, as both must be implemented, or neither.


To access the ID_AA64PFR0_EL1:

	
MRS <Xt>, ID_AA64PFR0_EL1 ; Read ID_AA64PFR0_EL1 into Xt

Register access is encoded as follows:

Table 4.51. ID_AA64PFR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0100 000

Was this page helpful? Yes No