The ID_AA64PFR0_EL1 characteristics are:
Provides additional information about implemented processor features in AArch64.
The optional Advanced SIMD and Floating-point extension is not included in the base product of the processor. ARM requires licensees to have contractual rights to obtain the Advanced SIMD and Floating-point extension.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_AA64PFR0_EL1 is architecturally mapped to external register ID_AA64PFR0_EL1.
ID_AA64PFR0_EL1 is a 64-bit register.
Figure 4.17 shows the ID_AA64PFR0_EL1 bit assignments.
Table 4.50 shows the ID_AA64PFR0_EL1 bit assignments.
GIC CPU interface:
Floating-point. The possible values are:
Advanced SIMD. The possible values are:
EL3 exception handling:
EL2 exception handling:
EL1 exception handling. The possible values are:
EL0 exception handling. The possible values are:
[a] The FP and AdvSIMD both take the same value, as both must be implemented, or neither.
To access the ID_AA64PFR0_EL1:
MRS <Xt>, ID_AA64PFR0_EL1 ; Read ID_AA64PFR0_EL1 into Xt
Register access is encoded as follows: