The CPACR_EL1 characteristics are:
Controls access to trace functionality and access to registers associated with Advanced SIMD and Floating-point execution.
CPACR_EL1 is part of the Other system registers functional group.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RW RW RW RW RW
CPACR_EL1 is architecturally mapped to AArch32 register CPACR. See Architectural Feature Access Control Register.
CPACR_EL1 is a 32-bit register.
Figure 4.31 shows the CPACR_EL1 bit assignments.
Table 4.75 shows the CPACR_EL1 bit assignments.
Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1.
This bit is res0.
Traps instructions that access registers
associated with Advanced SIMD and Floating-point execution to trap
to EL1 when executed from EL0 or EL1. The possible values are:
This field is res0 if Advanced SIMD and Floating-point are not implemented.
To access the CPACR_EL1:
MRS <Xt>, CPACR_EL1 ; Read CPACR_EL1 into Xt MSR CPACR_EL1, <Xt> ; Write Xt to CPACR_EL1