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Architectural Feature Access Control Register

The CPACR_EL1 characteristics are:

Purpose

Controls access to trace functionality and access to registers associated with Advanced SIMD and Floating-point execution.

CPACR_EL1 is part of the Other system registers functional group.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RW RW RW RW RW
Configurations

CPACR_EL1 is architecturally mapped to AArch32 register CPACR. See Architectural Feature Access Control Register.

Attributes

CPACR_EL1 is a 32-bit register.

Figure 4.31 shows the CPACR_EL1 bit assignments.

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Table 4.75 shows the CPACR_EL1 bit assignments.

Table 4.75. CPACR_EL1 bit assignments
Bits Name Function
[31:29] -

Reserved, res0.

[28] TTA

Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1.

This bit is res0.

[27:22] -

Reserved, res0.

[21:20] FPEN

Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1. The possible values are:

0bX0

Trap any instruction in EL0 or EL1 that uses registers associated with Advanced SIMD and Floating-point execution. The reset value is 0b00.

0b01

Trap any instruction in EL0 that uses registers associated with Advanced SIMD and Floating-point execution. Instructions in EL1 are not trapped.

0b11

No instructions are trapped.

This field is res0 if Advanced SIMD and Floating-point are not implemented.

[19:0] - Reserved, res0.

To access the CPACR_EL1:

	
MRS <Xt>, CPACR_EL1 ; Read CPACR_EL1 into Xt
MSR CPACR_EL1, <Xt> ; Write Xt to CPACR_EL1
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