You copied the Doc URL to your clipboard.

Architectural Feature Trap Register, EL2

The CPTR_EL2 characteristics are:

Purpose

Controls trapping to EL2 for accesses to CPACR, Trace functionality and registers associated with Advanced SIMD and Floating-point execution. Controls EL2 access to this functionality.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - - RW RW RW
Configurations

CPTR_EL2 is architecturally mapped to AArch32 register HCPTR. See Hyp Architectural Feature Trap Register.

Attributes

CPTR_EL2 is a 32-bit register.

Figure 4.35 shows the CPTR_EL2 bit assignments.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.79 shows the CPTR_EL2 bit assignments.

Table 4.79.  CPTR_EL2 bit assignments
Bits Name Function
[31] TCPAC

Traps direct access to CPACR from Non-secure EL1 to EL2. The possible values are:

0

Access to CPACR is not trapped. This is the reset value.

1

Access to CPACR is trapped.

[30:21] -

Reserved, res0.

[20] TTA

Trap Trace Access.

Not implemented. res0.

[19:14] -

Reserved, res0.

[13:12] - Reserved, res1.
[11] -

Reserved, res0.

[10] TFP

Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2, unless trapped to EL1. The possible values are:

0

Instructions are not trapped. This is the reset value if Advanced SIMD and Floating-point are implemented.

1

Instructions are trapped. This is always the value if Advanced SIMD and Floating-point are not implemented.

[9:0] -

Reserved, res1.


To access the CPTR_EL2:

	
MRS <Xt>, CPTR_EL2 ; Read CPTR_EL2 into Xt
MSR CPTR_EL2, <Xt> ; Write Xt to CPTR_EL2
Was this page helpful? Yes No