The CPTR_EL2 characteristics are:
Controls trapping to EL2 for accesses to CPACR, Trace functionality and registers associated with Advanced SIMD and Floating-point execution. Controls EL2 access to this functionality.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - RW RW RW
CPTR_EL2 is architecturally mapped to AArch32 register HCPTR. See Hyp Architectural Feature Trap Register.
CPTR_EL2 is a 32-bit register.
Figure 4.35 shows the CPTR_EL2 bit assignments.
Table 4.79 shows the CPTR_EL2 bit assignments.
Traps direct access to CPACR from Non-secure EL1 to EL2. The possible values are:
Trap Trace Access.
Not implemented. res0.
Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2, unless trapped to EL1. The possible values are:
To access the CPTR_EL2:
MRS <Xt>, CPTR_EL2 ; Read CPTR_EL2 into Xt MSR CPTR_EL2, <Xt> ; Write Xt to CPTR_EL2